Bringup-Bench is a collection of standalone minimal library and system dependence benchmarks useful for bringing up newly designed CPUs, accelerators, compilers and operating systems. You probably …

SystemVerilog parser library fully compliant with IEEE 1800-2017

A curated list of awesome things related to learning Zero-Knowledge Proofs (ZKP).

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

Icarus Verilog

Verilog AXI stream components for FPGA implementation

AXI interface modules for Cocotb

Fully opensource spiking neural network accelerator

Unit testing for cocotb

zkEVM prover in C++

AMD OpenNIC Project Overview

A STARK prover and verifier for arbitrary computations

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

Readings in Computer Architectures

CES VHDL utility library, with packages, memories, FIFOs, Clock Domain Crossing and more useful VHDL modules

Decompression of GZIP files for Xilinx Alveo

Python library for parsing module definitions and instantiations from SystemVerilog files

An acceleration engine for proving SNARKS over the bn128 curve, targeted for AWS FPGAs

This project implements a convolution kernel based on vivado HLS on zcu104

Squeezenet V1.1 on Cyclone V SoC-FPGA at 450ms/image, 20x faster than ARM A9 processor alone. A project for 2017 Innovate FPGA design contest.