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Multiple dispatch over abstract array types in JAX.
a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communication and Crypto applications
SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype
AdderNet ResNet20 for cifar10 written in SpinalHDL
CNN accelerator implemented with Spinal HDL
FPGA friendly Multiport memories (N-read-M-write) based on LVT
[HPCA'21] SpAtten: Efficient Sparse Attention Architecture with Cascade Token and Head Pruning
Implementation of the "Online learning of long-range dependencies" paper, NeurIPS 2023
[CVPRW '23] Real-time depth estimation with an event camera and a laser projector
ODIN online-learning digital spiking neural network (SNN) processor - HDL source code and documentation.
Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
Project Apicula 🐝: bitstream documentation for Gowin FPGAs
Rust crate for physics simulation based on the Bullet SDK and modeled after PyBullet (Github Mirror).
The fastest and most memory efficient lattice Boltzmann CFD software, running on all GPUs and CPUs via OpenCL. Free for non-commercial use.
Port forwarding utility written in Rust with IP and TLS SNI/ALPN-based forwarding rules, multiple targets per port, iptables support, and hot reloading.