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Commits on Mar 14, 2015

• x86: fix Immediate operand size when first register operand is embedded in mnemonic (CMP8i8). bug reported by @joelpx

  aquynh

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Commits on Mar 11, 2015

• Merge branch 'v3' of https://github.com/aquynh/capstone into v3

  aquynh

  committed
  97447d1

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• x86: F2 can be a part of instruction encoding, but not a prefix

  aquynh

  committed
  d50dcc5

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Commits on Mar 10, 2015

• arm: more optimization on MCInstrDesc struct to reduce the library size by further 20KB

  aquynh

  committed
  726ade0

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• arm: rever the change on OperandInfo* in the last commit

  aquynh

  committed
  e220b50

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• optimize MCInstrDesc to reduce its size

  aquynh

  committed
  3d00666

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• sparc, systemz, xcore: getInstruction() should return boolean instead of DecodeStatus

  aquynh

  committed
  7d5266d

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Commits on Mar 7, 2015

• x86: multiple fixes for insns[] - reduced mode (X86Mapping.c)

  aquynh

  committed
  5160e23

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• x86: multiple fixes for insns[] (X86Mapping.c)

  aquynh

  committed
  c0fa5b7

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Commits on Mar 3, 2015

• Merge branch 'master' into v3

  aquynh

  committed
  7334a88

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• Silencing Clang warning about losing precision

  fay59

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• Silencing uninitialized variable warning about insn_id

  fay59

  committed
  e255659

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• Silencing Clang warning bys casting values

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  fay59

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Commits on Feb 27, 2015

• mips: sanity check for input code length of Mips64

  aquynh

  committed
  fbfa06d

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Commits on Feb 25, 2015

• x86: allow prefixes to be positioned anywhere. this should fix the bug reported by Gabriel Quadros

  aquynh

  committed
  ed46b0b

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• arm: fix some warnings reported by MSVC

  aquynh

  committed
  b756aed

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• arm: fix some warnings reported by MSVC

  aquynh

  committed
  8c9fd12

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Commits on Feb 15, 2015

• Correct printAM3PreOrOffsetIndexOp disp value

  

  pzread

  authored and

  aquynh

  committed
  5598301

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• Correct printAM3PreOrOffsetIndexOp disp value

  pzread

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  996f06c

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Commits on Feb 14, 2015

• Remove incorrect ITBlock.size = 0

  pzread

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Commits on Feb 13, 2015

• x86: REPNE can go with STOS/MOVS. bug reported by Gabriel Quadros

  aquynh

  committed
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Commits on Feb 12, 2015

• x86: add the missing X86 instructions in X86_REDUCE mode in X86DisassemblerDecoder.c. bug reported by Julian Stecklina

  aquynh

  committed
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Commits on Feb 10, 2015

• x86: fix operand size for 'CALL PTR [REG]'. bug reported by Gabriel Quadros

  aquynh

  committed
  e10b53f

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Commits on Jan 21, 2015

• arm: add few more post-indexed instructions doing writeback

  aquynh

  committed
  9426ad5

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• arm: fix a bug in the last commit

  aquynh

  committed
  7bbb433

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• arm: some load/store instructions writeback without bang letter. bug reported by @jabba2989

  aquynh

  committed
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Commits on Jan 13, 2015

• arm: in Thumb mode, ADC & SBC do not update flags. bug reported by @jabba2989

  aquynh

  committed
  f2157de

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• x86: remove some instructions unsupported in 3.x version

  aquynh

  committed
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• arm64 & sparc: fix some warnings reported by MSVC

  aquynh

  committed
  273c6f4

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• x86: remove some instructions irrelevant for LOCK prefix in invalidPrefix()

  aquynh

  committed
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• x86: properly handle REP, REPNE & REPNZ prefixes

  aquynh

  committed
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• x86: add more valid instructions for LOCK prefix

  

  Andrew Wesie

  authored and

  aquynh

  committed
  29f41da

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• x86: check for invalid instructions with LOCK prefix

  aquynh

  committed
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• Merge branch 'v3' of https://github.com/aquynh/capstone into v3

  aquynh

  committed
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• arm64: BL & BLR do not read SP register

  aquynh

  committed
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