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Hexagon: Add multiclass/encoding bits for the New-Value Jump instruct…
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…ions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180953 91177308-0d34-0410-b5e6-96231b3b80d8
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@JyotsnaVerma
JyotsnaVerma committed May 2, 2013
1 parent 556dd3a commit 8a3f500
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Showing 5 changed files with 305 additions and 404 deletions.
24 changes: 24 additions & 0 deletions lib/Target/Hexagon/Hexagon.td
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Original file line number Diff line number Diff line change
Expand Up @@ -83,6 +83,30 @@ def getPredOpcode : InstrMapping {
let ValueCols = [["true"], ["false"]];
}

//===----------------------------------------------------------------------===//
// Generate mapping table to relate predicate-true instructions with their
// predicate-false forms
//
def getFalsePredOpcode : InstrMapping {
let FilterClass = "PredRel";
let RowFields = ["BaseOpcode", "PNewValue", "isNVStore", "isBrTaken"];
let ColFields = ["PredSense"];
let KeyCol = ["true"];
let ValueCols = [["false"]];
}

//===----------------------------------------------------------------------===//
// Generate mapping table to relate predicate-false instructions with their
// predicate-true forms
//
def getTruePredOpcode : InstrMapping {
let FilterClass = "PredRel";
let RowFields = ["BaseOpcode", "PNewValue", "isNVStore", "isBrTaken"];
let ColFields = ["PredSense"];
let KeyCol = ["false"];
let ValueCols = [["true"]];
}

//===----------------------------------------------------------------------===//
// Generate mapping table to relate predicated instructions with their .new
// format.
Expand Down
279 changes: 57 additions & 222 deletions lib/Target/Hexagon/HexagonInstrInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -625,110 +625,8 @@ bool HexagonInstrInfo::isExtended(const MachineInstr *MI) const {
return false;
}

bool HexagonInstrInfo::isNewValueJump(const MachineInstr *MI) const {
switch (MI->getOpcode()) {
default: return false;
// JMP_EQri
case Hexagon::JMP_EQriPt_nv_V4:
case Hexagon::JMP_EQriPnt_nv_V4:
case Hexagon::JMP_EQriNotPt_nv_V4:
case Hexagon::JMP_EQriNotPnt_nv_V4:
case Hexagon::JMP_EQriPt_ie_nv_V4:
case Hexagon::JMP_EQriPnt_ie_nv_V4:
case Hexagon::JMP_EQriNotPt_ie_nv_V4:
case Hexagon::JMP_EQriNotPnt_ie_nv_V4:

// JMP_EQri - with -1
case Hexagon::JMP_EQriPtneg_nv_V4:
case Hexagon::JMP_EQriPntneg_nv_V4:
case Hexagon::JMP_EQriNotPtneg_nv_V4:
case Hexagon::JMP_EQriNotPntneg_nv_V4:
case Hexagon::JMP_EQriPtneg_ie_nv_V4:
case Hexagon::JMP_EQriPntneg_ie_nv_V4:
case Hexagon::JMP_EQriNotPtneg_ie_nv_V4:
case Hexagon::JMP_EQriNotPntneg_ie_nv_V4:

// JMP_EQrr
case Hexagon::JMP_EQrrPt_nv_V4:
case Hexagon::JMP_EQrrPnt_nv_V4:
case Hexagon::JMP_EQrrNotPt_nv_V4:
case Hexagon::JMP_EQrrNotPnt_nv_V4:
case Hexagon::JMP_EQrrPt_ie_nv_V4:
case Hexagon::JMP_EQrrPnt_ie_nv_V4:
case Hexagon::JMP_EQrrNotPt_ie_nv_V4:
case Hexagon::JMP_EQrrNotPnt_ie_nv_V4:

// JMP_GTri
case Hexagon::JMP_GTriPt_nv_V4:
case Hexagon::JMP_GTriPnt_nv_V4:
case Hexagon::JMP_GTriNotPt_nv_V4:
case Hexagon::JMP_GTriNotPnt_nv_V4:
case Hexagon::JMP_GTriPt_ie_nv_V4:
case Hexagon::JMP_GTriPnt_ie_nv_V4:
case Hexagon::JMP_GTriNotPt_ie_nv_V4:
case Hexagon::JMP_GTriNotPnt_ie_nv_V4:

// JMP_GTri - with -1
case Hexagon::JMP_GTriPtneg_nv_V4:
case Hexagon::JMP_GTriPntneg_nv_V4:
case Hexagon::JMP_GTriNotPtneg_nv_V4:
case Hexagon::JMP_GTriNotPntneg_nv_V4:
case Hexagon::JMP_GTriPtneg_ie_nv_V4:
case Hexagon::JMP_GTriPntneg_ie_nv_V4:
case Hexagon::JMP_GTriNotPtneg_ie_nv_V4:
case Hexagon::JMP_GTriNotPntneg_ie_nv_V4:

// JMP_GTrr
case Hexagon::JMP_GTrrPt_nv_V4:
case Hexagon::JMP_GTrrPnt_nv_V4:
case Hexagon::JMP_GTrrNotPt_nv_V4:
case Hexagon::JMP_GTrrNotPnt_nv_V4:
case Hexagon::JMP_GTrrPt_ie_nv_V4:
case Hexagon::JMP_GTrrPnt_ie_nv_V4:
case Hexagon::JMP_GTrrNotPt_ie_nv_V4:
case Hexagon::JMP_GTrrNotPnt_ie_nv_V4:

// JMP_GTrrdn
case Hexagon::JMP_GTrrdnPt_nv_V4:
case Hexagon::JMP_GTrrdnPnt_nv_V4:
case Hexagon::JMP_GTrrdnNotPt_nv_V4:
case Hexagon::JMP_GTrrdnNotPnt_nv_V4:
case Hexagon::JMP_GTrrdnPt_ie_nv_V4:
case Hexagon::JMP_GTrrdnPnt_ie_nv_V4:
case Hexagon::JMP_GTrrdnNotPt_ie_nv_V4:
case Hexagon::JMP_GTrrdnNotPnt_ie_nv_V4:

// JMP_GTUri
case Hexagon::JMP_GTUriPt_nv_V4:
case Hexagon::JMP_GTUriPnt_nv_V4:
case Hexagon::JMP_GTUriNotPt_nv_V4:
case Hexagon::JMP_GTUriNotPnt_nv_V4:
case Hexagon::JMP_GTUriPt_ie_nv_V4:
case Hexagon::JMP_GTUriPnt_ie_nv_V4:
case Hexagon::JMP_GTUriNotPt_ie_nv_V4:
case Hexagon::JMP_GTUriNotPnt_ie_nv_V4:

// JMP_GTUrr
case Hexagon::JMP_GTUrrPt_nv_V4:
case Hexagon::JMP_GTUrrPnt_nv_V4:
case Hexagon::JMP_GTUrrNotPt_nv_V4:
case Hexagon::JMP_GTUrrNotPnt_nv_V4:
case Hexagon::JMP_GTUrrPt_ie_nv_V4:
case Hexagon::JMP_GTUrrPnt_ie_nv_V4:
case Hexagon::JMP_GTUrrNotPt_ie_nv_V4:
case Hexagon::JMP_GTUrrNotPnt_ie_nv_V4:

// JMP_GTUrrdn
case Hexagon::JMP_GTUrrdnPt_nv_V4:
case Hexagon::JMP_GTUrrdnPnt_nv_V4:
case Hexagon::JMP_GTUrrdnNotPt_nv_V4:
case Hexagon::JMP_GTUrrdnNotPnt_nv_V4:
case Hexagon::JMP_GTUrrdnPt_ie_nv_V4:
case Hexagon::JMP_GTUrrdnPnt_ie_nv_V4:
case Hexagon::JMP_GTUrrdnNotPt_ie_nv_V4:
case Hexagon::JMP_GTUrrdnNotPnt_ie_nv_V4:
return true;
}
bool HexagonInstrInfo::isBranch (const MachineInstr *MI) const {
return MI->getDesc().isBranch();
}

bool HexagonInstrInfo::isNewValueStore(const MachineInstr *MI) const {
Expand Down Expand Up @@ -1032,6 +930,12 @@ bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const {
// cNotPt ---> cNotPt_nv
// cPt ---> cPt_nv
unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const {
int InvPredOpcode;
InvPredOpcode = isPredicatedTrue(Opc) ? Hexagon::getFalsePredOpcode(Opc)
: Hexagon::getTruePredOpcode(Opc);
if (InvPredOpcode >= 0) // Valid instruction with the inverted predicate.
return InvPredOpcode;

switch(Opc) {
default: llvm_unreachable("Unexpected predicated instruction");
case Hexagon::TFR_cPt:
Expand Down Expand Up @@ -1364,117 +1268,6 @@ unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const {
return Hexagon::DEALLOC_RET_cNotPt_V4;
case Hexagon::DEALLOC_RET_cNotPt_V4:
return Hexagon::DEALLOC_RET_cPt_V4;

// New Value Jump.
// JMPEQ_ri - with -1.
case Hexagon::JMP_EQriPtneg_nv_V4:
return Hexagon::JMP_EQriNotPtneg_nv_V4;
case Hexagon::JMP_EQriNotPtneg_nv_V4:
return Hexagon::JMP_EQriPtneg_nv_V4;

case Hexagon::JMP_EQriPntneg_nv_V4:
return Hexagon::JMP_EQriNotPntneg_nv_V4;
case Hexagon::JMP_EQriNotPntneg_nv_V4:
return Hexagon::JMP_EQriPntneg_nv_V4;

// JMPEQ_ri.
case Hexagon::JMP_EQriPt_nv_V4:
return Hexagon::JMP_EQriNotPt_nv_V4;
case Hexagon::JMP_EQriNotPt_nv_V4:
return Hexagon::JMP_EQriPt_nv_V4;

case Hexagon::JMP_EQriPnt_nv_V4:
return Hexagon::JMP_EQriNotPnt_nv_V4;
case Hexagon::JMP_EQriNotPnt_nv_V4:
return Hexagon::JMP_EQriPnt_nv_V4;

// JMPEQ_rr.
case Hexagon::JMP_EQrrPt_nv_V4:
return Hexagon::JMP_EQrrNotPt_nv_V4;
case Hexagon::JMP_EQrrNotPt_nv_V4:
return Hexagon::JMP_EQrrPt_nv_V4;

case Hexagon::JMP_EQrrPnt_nv_V4:
return Hexagon::JMP_EQrrNotPnt_nv_V4;
case Hexagon::JMP_EQrrNotPnt_nv_V4:
return Hexagon::JMP_EQrrPnt_nv_V4;

// JMPGT_ri - with -1.
case Hexagon::JMP_GTriPtneg_nv_V4:
return Hexagon::JMP_GTriNotPtneg_nv_V4;
case Hexagon::JMP_GTriNotPtneg_nv_V4:
return Hexagon::JMP_GTriPtneg_nv_V4;

case Hexagon::JMP_GTriPntneg_nv_V4:
return Hexagon::JMP_GTriNotPntneg_nv_V4;
case Hexagon::JMP_GTriNotPntneg_nv_V4:
return Hexagon::JMP_GTriPntneg_nv_V4;

// JMPGT_ri.
case Hexagon::JMP_GTriPt_nv_V4:
return Hexagon::JMP_GTriNotPt_nv_V4;
case Hexagon::JMP_GTriNotPt_nv_V4:
return Hexagon::JMP_GTriPt_nv_V4;

case Hexagon::JMP_GTriPnt_nv_V4:
return Hexagon::JMP_GTriNotPnt_nv_V4;
case Hexagon::JMP_GTriNotPnt_nv_V4:
return Hexagon::JMP_GTriPnt_nv_V4;

// JMPGT_rr.
case Hexagon::JMP_GTrrPt_nv_V4:
return Hexagon::JMP_GTrrNotPt_nv_V4;
case Hexagon::JMP_GTrrNotPt_nv_V4:
return Hexagon::JMP_GTrrPt_nv_V4;

case Hexagon::JMP_GTrrPnt_nv_V4:
return Hexagon::JMP_GTrrNotPnt_nv_V4;
case Hexagon::JMP_GTrrNotPnt_nv_V4:
return Hexagon::JMP_GTrrPnt_nv_V4;

// JMPGT_rrdn.
case Hexagon::JMP_GTrrdnPt_nv_V4:
return Hexagon::JMP_GTrrdnNotPt_nv_V4;
case Hexagon::JMP_GTrrdnNotPt_nv_V4:
return Hexagon::JMP_GTrrdnPt_nv_V4;

case Hexagon::JMP_GTrrdnPnt_nv_V4:
return Hexagon::JMP_GTrrdnNotPnt_nv_V4;
case Hexagon::JMP_GTrrdnNotPnt_nv_V4:
return Hexagon::JMP_GTrrdnPnt_nv_V4;

// JMPGTU_ri.
case Hexagon::JMP_GTUriPt_nv_V4:
return Hexagon::JMP_GTUriNotPt_nv_V4;
case Hexagon::JMP_GTUriNotPt_nv_V4:
return Hexagon::JMP_GTUriPt_nv_V4;

case Hexagon::JMP_GTUriPnt_nv_V4:
return Hexagon::JMP_GTUriNotPnt_nv_V4;
case Hexagon::JMP_GTUriNotPnt_nv_V4:
return Hexagon::JMP_GTUriPnt_nv_V4;

// JMPGTU_rr.
case Hexagon::JMP_GTUrrPt_nv_V4:
return Hexagon::JMP_GTUrrNotPt_nv_V4;
case Hexagon::JMP_GTUrrNotPt_nv_V4:
return Hexagon::JMP_GTUrrPt_nv_V4;

case Hexagon::JMP_GTUrrPnt_nv_V4:
return Hexagon::JMP_GTUrrNotPnt_nv_V4;
case Hexagon::JMP_GTUrrNotPnt_nv_V4:
return Hexagon::JMP_GTUrrPnt_nv_V4;

// JMPGTU_rrdn.
case Hexagon::JMP_GTUrrdnPt_nv_V4:
return Hexagon::JMP_GTUrrdnNotPt_nv_V4;
case Hexagon::JMP_GTUrrdnNotPt_nv_V4:
return Hexagon::JMP_GTUrrdnPt_nv_V4;

case Hexagon::JMP_GTUrrdnPnt_nv_V4:
return Hexagon::JMP_GTUrrdnNotPnt_nv_V4;
case Hexagon::JMP_GTUrrdnNotPnt_nv_V4:
return Hexagon::JMP_GTUrrdnPnt_nv_V4;
}
}

Expand Down Expand Up @@ -1503,12 +1296,7 @@ getMatchingCondBranchOpcode(int Opc, bool invertPredicate) const {
case Hexagon::JMP:
return !invertPredicate ? Hexagon::JMP_t :
Hexagon::JMP_f;
case Hexagon::JMP_EQrrPt_nv_V4:
return !invertPredicate ? Hexagon::JMP_EQrrPt_nv_V4 :
Hexagon::JMP_EQrrNotPt_nv_V4;
case Hexagon::JMP_EQriPt_nv_V4:
return !invertPredicate ? Hexagon::JMP_EQriPt_nv_V4 :
Hexagon::JMP_EQriNotPt_nv_V4;

case Hexagon::COMBINE_rr:
return !invertPredicate ? Hexagon::COMBINE_rr_cPt :
Hexagon::COMBINE_rr_cNotPt;
Expand Down Expand Up @@ -1889,20 +1677,55 @@ isProfitableToIfCvt(MachineBasicBlock &TMBB,
return true;
}


// Returns true if an instruction is predicated irrespective of the predicate
// sense. For example, all of the following will return true.
// if (p0) R1 = add(R2, R3)
// if (!p0) R1 = add(R2, R3)
// if (p0.new) R1 = add(R2, R3)
// if (!p0.new) R1 = add(R2, R3)
bool HexagonInstrInfo::isPredicated(const MachineInstr *MI) const {
const uint64_t F = MI->getDesc().TSFlags;

return ((F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
}

bool HexagonInstrInfo::isPredicated(unsigned Opcode) const {
const uint64_t F = get(Opcode).TSFlags;

return ((F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
}

bool HexagonInstrInfo::isPredicatedTrue(const MachineInstr *MI) const {
const uint64_t F = MI->getDesc().TSFlags;

assert(isPredicated(MI));
return (!((F >> HexagonII::PredicatedFalsePos) &
HexagonII::PredicatedFalseMask));
}

bool HexagonInstrInfo::isPredicatedTrue(unsigned Opcode) const {
const uint64_t F = get(Opcode).TSFlags;

// Make sure that the instruction is predicated.
assert((F>> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
return (!((F >> HexagonII::PredicatedFalsePos) &
HexagonII::PredicatedFalseMask));
}

bool HexagonInstrInfo::isPredicatedNew(const MachineInstr *MI) const {
const uint64_t F = MI->getDesc().TSFlags;

assert(isPredicated(MI));
return ((F >> HexagonII::PredicatedNewPos) & HexagonII::PredicatedNewMask);
}

bool HexagonInstrInfo::isPredicatedNew(unsigned Opcode) const {
const uint64_t F = get(Opcode).TSFlags;

assert(isPredicated(Opcode));
return ((F >> HexagonII::PredicatedNewPos) & HexagonII::PredicatedNewMask);
}

bool
HexagonInstrInfo::DefinesPredicate(MachineInstr *MI,
std::vector<MachineOperand> &Pred) const {
Expand Down Expand Up @@ -2371,6 +2194,18 @@ isConditionalStore (const MachineInstr* MI) const {
}
}


bool HexagonInstrInfo::isNewValueJump(const MachineInstr *MI) const {
if (isNewValue(MI) && isBranch(MI))
return true;
return false;
}

bool HexagonInstrInfo::isNewValue(const MachineInstr* MI) const {
const uint64_t F = MI->getDesc().TSFlags;
return ((F >> HexagonII::NewValuePos) & HexagonII::NewValueMask);
}

// Returns true, if any one of the operands is a dot new
// insn, whether it is predicated dot new or register dot new.
bool HexagonInstrInfo::isDotNewInst (const MachineInstr* MI) const {
Expand Down
6 changes: 6 additions & 0 deletions lib/Target/Hexagon/HexagonInstrInfo.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -113,6 +113,7 @@ class HexagonInstrInfo : public HexagonGenInstrInfo {

unsigned createVR(MachineFunction* MF, MVT VT) const;

virtual bool isBranch(const MachineInstr *MI) const;
virtual bool isPredicable(MachineInstr *MI) const;
virtual bool
PredicateInstruction(MachineInstr *MI,
Expand All @@ -129,7 +130,11 @@ class HexagonInstrInfo : public HexagonGenInstrInfo {
const BranchProbability &Probability) const;

virtual bool isPredicated(const MachineInstr *MI) const;
virtual bool isPredicated(unsigned Opcode) const;
virtual bool isPredicatedTrue(const MachineInstr *MI) const;
virtual bool isPredicatedTrue(unsigned Opcode) const;
virtual bool isPredicatedNew(const MachineInstr *MI) const;
virtual bool isPredicatedNew(unsigned Opcode) const;
virtual bool DefinesPredicate(MachineInstr *MI,
std::vector<MachineOperand> &Pred) const;
virtual bool
Expand Down Expand Up @@ -178,6 +183,7 @@ class HexagonInstrInfo : public HexagonGenInstrInfo {
bool isConditionalLoad (const MachineInstr* MI) const;
bool isConditionalStore(const MachineInstr* MI) const;
bool isNewValueInst(const MachineInstr* MI) const;
bool isNewValue(const MachineInstr* MI) const;
bool isDotNewInst(const MachineInstr* MI) const;
bool isDeallocRet(const MachineInstr *MI) const;
unsigned getInvertedPredicatedOpcode(const int Opc) const;
Expand Down
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