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[x86] fix formatting; NFCI
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304576 91177308-0d34-0410-b5e6-96231b3b80d8
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rotateright committed Jun 2, 2017
1 parent 7796b91 commit f1a1cf1
Showing 1 changed file with 9 additions and 8 deletions.
17 changes: 9 additions & 8 deletions lib/Target/X86/X86ISelLowering.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -17144,7 +17144,7 @@ static SDValue LowerVSETCC(SDValue Op, const X86Subtarget &Subtarget,
DAG.getConstant(CmpMode, dl, MVT::i8));
}

// We are handling one of the integer comparisons here. Since SSE only has
// We are handling one of the integer comparisons here. Since SSE only has
// GT and EQ comparisons for integer, swapping operands and multiple
// operations may be required for some comparisons.
unsigned Opc;
Expand All @@ -17170,22 +17170,23 @@ static SDValue LowerVSETCC(SDValue Op, const X86Subtarget &Subtarget,

// Special case: Use min/max operations for SETULE/SETUGE
MVT VET = VT.getVectorElementType();
bool hasMinMax =
(Subtarget.hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
|| (Subtarget.hasSSE2() && (VET == MVT::i8));
bool HasMinMax =
(Subtarget.hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32)) ||
(Subtarget.hasSSE2() && (VET == MVT::i8));

if (hasMinMax) {
if (HasMinMax) {
switch (SetCCOpcode) {
default: break;
case ISD::SETULE: Opc = ISD::UMIN; MinMax = true; break;
case ISD::SETUGE: Opc = ISD::UMAX; MinMax = true; break;
}

if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
if (MinMax)
Swap = Invert = FlipSigns = false;
}

bool hasSubus = Subtarget.hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
if (!MinMax && hasSubus) {
bool HasSubus = Subtarget.hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
if (!MinMax && HasSubus) {
// As another special case, use PSUBUS[BW] when it's profitable. E.g. for
// Op0 u<= Op1:
// t = psubus Op0, Op1
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