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Still no response from source, committing before attemping FFI
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@fmckeogh
fmckeogh committed May 24, 2023
1 parent 54508e1 commit 1f0202d
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Showing 5 changed files with 120 additions and 68 deletions.
14 changes: 7 additions & 7 deletions Cargo.lock
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10 changes: 8 additions & 2 deletions bridge/src/main.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -19,7 +19,7 @@ mod app {
rgb::{Color, Rgb},
},
bitbang_hal::i2c::I2cBB,
defmt::info,
defmt::{info, trace},
fusb302b::Fusb302b,
stm32f0xx_hal::{
gpio::{
Expand Down Expand Up @@ -48,7 +48,12 @@ mod app {
#[init]
fn init(cx: init::Context) -> (Shared, Local, init::Monotonics) {
let mut flash = cx.device.FLASH;
let mut rcc = cx.device.RCC.configure().freeze(&mut flash);
let mut rcc = cx
.device
.RCC
.configure()
.sysclk(32u32.mhz())
.freeze(&mut flash);

let mono = Systick::new(cx.core.SYST, rcc.clocks.sysclk().0);

Expand Down Expand Up @@ -109,6 +114,7 @@ fn callback(event: Event) -> Option<Response> {
unsafe { IS_CONNECTED = true };
}
Event::PowerRejected => trace!("power rejected"),

Event::PowerReady { active_voltage_mv } => trace!("power ready {}mV", active_voltage_mv),

Event::SourceCapabilities {
Expand Down
142 changes: 92 additions & 50 deletions fusb302b/src/lib.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -10,7 +10,7 @@ use {
},
timeout::Timeout,
},
byteorder::{ByteOrder, LittleEndian},
byteorder::{BigEndian, ByteOrder, LittleEndian},
defmt::{error, trace, Format},
embedded_hal::blocking::i2c::{Read, Write, WriteRead},
fixed_queue::VecDeque,
Expand Down Expand Up @@ -88,7 +88,7 @@ impl<I2C: Read + Write + WriteRead> Fusb302b<I2C> {
.with_bandgap_wake(true)
.with_measure_block(true)
.with_receiver(true)
.with_internal_oscillator(false),
.with_internal_oscillator(true),
);

// disable CC monitoring
Expand Down Expand Up @@ -184,13 +184,16 @@ impl<I2C: Read + Write + WriteRead> Fusb302b<I2C> {
);

// // Enable interrupts for CC activity and CRC_CHK
// write_register(reg_mask, mask_m_all & ~(mask_m_activity | mask_m_crc_chk));
//write_register(reg_mask, mask_m_all & ~(mask_m_activity | mask_m_crc_chk));
self.registers.set_mask1(Mask1(255 & !(64 | 16)));

// // Unmask all interrupts (toggle done, hard reset, tx sent etc.)
// write_register(reg_maska, maska_m_none);
self.registers.set_mask_a(MaskA(0));

// // Enable good CRC sent interrupt
// write_register(reg_maskb, maskb_m_none);
self.registers.set_mask_b(MaskB(0));

// Enable pull down and CC monitoring

Expand Down Expand Up @@ -262,10 +265,10 @@ impl<I2C: Read + Write + WriteRead> Fusb302b<I2C> {
trace!("tx ack");

// turn off internal oscillator if TX FIFO is empty
if self.registers.status1().tx_empty() {
let power = self.registers.power().with_internal_oscillator(false);
self.registers.set_power(power);
}
// if self.registers.status1().tx_empty() {
// let power = self.registers.power().with_internal_oscillator(false);
// self.registers.set_power(power);
// }
}

if interrupt.i_activity() {
Expand All @@ -288,9 +291,9 @@ impl<I2C: Read + Write + WriteRead> Fusb302b<I2C> {
}

fn read_messages(&mut self) {
trace!("reading messages");

while !self.registers.status1().rx_empty() {
trace!("rx not empty, reading messages");

// read message
let mut buf = [0u8; 3];
self.registers.read_fifo(&mut buf);
Expand Down Expand Up @@ -321,6 +324,7 @@ impl<I2C: Read + Write + WriteRead> Fusb302b<I2C> {
let State::Connected { events } = &mut self.state else { panic!() };

let msg = Message::parse(header, &payload);

trace!("got msg {:?}", msg);
events
.push_back(Event::MessageReceived(msg))
Expand Down Expand Up @@ -367,63 +371,101 @@ impl<I2C: Read + Write + WriteRead> Fusb302b<I2C> {
}
}

fn request_power(&mut self, index: usize, current: u16) {
fn request_power(&mut self, index: usize, mut current: u16) {
let payload = {
let mut payload = [0u8; 4];

LittleEndian::write_u32(
payload.as_mut_slice(),
FixedVariableRequestDataObject(0)
.with_operating_current(current)
.with_maximum_operating_current(current)
.with_object_position(index as u8)
.with_no_usb_suspend(true)
.with_usb_communications_capable(true)
.0,
);
let no_usb_suspend = 1;
let usb_comm_capable = 2;

if current > 0x3ff {
current = 0x3ff;
}
payload[0] = u8::try_from(current & 0xff).unwrap();
payload[1] = u8::try_from(((current >> 8) & 0x03) | ((current << 2) & 0xfc)).unwrap();
payload[2] = u8::try_from((current >> 6) & 0x0f).unwrap();
payload[3] =
u8::try_from((index & 0x07) << 4 | no_usb_suspend | usb_comm_capable).unwrap();

payload
};

let header = usb_pd::header::Header(0)
.with_message_type_raw(DataMessageType::Request as u8)
.with_num_objects(1)
.with_spec_revision(usb_pd::header::SpecificationRevision::R3_0)
.with_port_power_role(usb_pd::PowerRole::Sink)
.with_message_id(self.message_id_counter.next());
let header = ((1 & 0x07) << 12) | (130 & 0x1f) | 0x40 | ((2 - 1) << 6);
// let header = usb_pd::header::Header(0)
// .with_message_type_raw(DataMessageType::Request as u8)
// .with_num_objects(1)
// .with_spec_revision(usb_pd::header::SpecificationRevision::R3_0)
// .with_port_power_role(usb_pd::PowerRole::Sink)
// .with_message_id(self.message_id_counter.next());

self.send_message(header, payload.as_slice());
}

fn send_message(&mut self, header: Header, payload: &[u8]) {
self.registers.power().set_internal_oscillator(true);
self.registers.power().set_bandgap_wake(true);
self.registers.power().set_measure_block(true);
self.registers.power().set_receiver(true);

let payload_length = header.num_objects() * 4;
fn send_message(&mut self, header: u16, payload: &[u8]) {
let payload_length = 1 * 4;

let mut buffer = [0u8; 40];
trace!(
"{} {}",
self.registers.status1().tx_empty(),
self.registers.status1().tx_full()
);

buffer[1] = Token::Sop1 as u8;
buffer[2] = Token::Sop1 as u8;
buffer[3] = Token::Sop1 as u8;
buffer[4] = Token::Sop2 as u8;
buffer[5] = Token::PackSym as u8 | (payload_length + 2);
buffer[6] = u8::try_from(header.0 & 0xff).unwrap();
buffer[7] = u8::try_from(header.0 >> 8).unwrap();
self.registers.write_fifo(&mut [
0x43, 18, 18, 18, 19, 134, 194, 16, 44, 177, 4, 19, 255, 20, 254, 161,
]);

buffer[8] = payload[0];
buffer[9] = payload[1];
buffer[10] = payload[2];
buffer[11] = payload[3];
trace!(
"{} {}",
self.registers.status1().tx_empty(),
self.registers.status1().tx_full()
);

buffer[12] = Token::JamCrc as u8;
buffer[13] = Token::Eop as u8;
buffer[14] = Token::TxOff as u8;
buffer[15] = Token::TxOn as u8;
// let control0 = self.registers.control0().with_tx_start(true);
// self.registers.set_control0(control0);

// self.registers.write_fifo(&mut [
// 0x43,
// Token::Sop1 as u8,
// Token::Sop1 as u8,
// Token::Sop1 as u8,
// Token::Sop2 as u8,
// Token::PackSym as u8 | (payload_length + 2),
// ]);

// self.registers.write_fifo(&mut [
// 0x43,
// u8::try_from(header & 0xff).unwrap(),
// u8::try_from(header >> 8).unwrap(),
// payload[0],
// payload[1],
// payload[2],
// payload[3],
// ]);

// trace!(
// "{} {}",
// self.registers.status1().tx_empty(),
// self.registers.status1().tx_full()
// );

// self.registers.write_fifo(&mut [
// 0x43,
// Token::JamCrc as u8,
// Token::Eop as u8,
// Token::TxOff as u8,
// Token::TxOn as u8,
// ]);

let control0 = self.registers.control0().with_tx_start(true);
self.registers.set_control0(control0);

trace!(
"{} {}",
self.registers.status1().tx_empty(),
self.registers.status1().tx_full()
);

self.registers.write_fifo(&mut buffer[..=15]);
trace!("sent message");

self.message_id_counter.inc();
}
Expand Down
20 changes: 11 additions & 9 deletions fusb302b/src/registers.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -4,6 +4,7 @@
use {
crate::DEVICE_ADDRESS,
defmt::{trace, Format},
embedded_hal::blocking::i2c::{Read, Write, WriteRead},
proc_bitfield::bitfield,
usb_pd::{DataRole, PowerRole},
Expand Down Expand Up @@ -86,26 +87,27 @@ impl<I2C: Read + Write + WriteRead> Registers<I2C> {
}

fn write_register_raw(&mut self, register: u8, value: u8) {
self.i2c.write(DEVICE_ADDRESS, &[register, value]).ok();
assert!(self.i2c.write(DEVICE_ADDRESS, &[register, value]).is_ok());
}

fn read_register_raw(&mut self, register: u8) -> u8 {
let mut buffer = [0u8];
self.i2c
assert!(self
.i2c
.write_read(DEVICE_ADDRESS, &[register], &mut buffer)
.ok();
.is_ok());
buffer[0]
}

pub fn read_fifo(&mut self, buf: &mut [u8]) {
self.i2c
assert!(self
.i2c
.write_read(DEVICE_ADDRESS, &[Register::Fifo as u8], buf)
.ok();
.is_ok());
}

pub fn write_fifo(&mut self, buf: &mut [u8]) {
buf[0] = Register::Fifo as u8;
self.i2c.write(DEVICE_ADDRESS, buf).ok();
assert!(self.i2c.write(DEVICE_ADDRESS, buf).is_ok());
}

generate_register_accessors!(
Expand Down Expand Up @@ -690,7 +692,7 @@ impl Default for InterruptB {
}

bitfield! {
#[derive(Clone, Copy, PartialEq, Eq)]
#[derive(Clone, Copy, PartialEq, Eq, Format)]
pub struct Status0(pub u8): FromRaw, IntoRaw {
/// Interrupt occurs when VBUS transitions through vVBUSthr. This bit typically is used to
/// recognize port partner during startup
Expand Down Expand Up @@ -743,7 +745,7 @@ impl Default for Status0 {
}

bitfield! {
#[derive(Clone, Copy, PartialEq, Eq)]
#[derive(Clone, Copy, PartialEq, Eq, Format)]
pub struct Status1(pub u8): FromRaw, IntoRaw {
/// Indicates the last packet placed in the RxFIFO is type SOP'' (SOP double prime)
pub rxsop2: bool [read_only] @ 7,
Expand Down
2 changes: 2 additions & 0 deletions usb-pd/src/header.rs
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Original file line number Diff line number Diff line change
@@ -1,6 +1,7 @@
use {
crate::{DataRole, PowerRole},
byteorder::{ByteOrder, LittleEndian},
defmt::Format,
proc_bitfield::bitfield,
};

Expand Down Expand Up @@ -33,6 +34,7 @@ impl Header {
}
}

#[derive(Format)]
pub enum SpecificationRevision {
R1_0,
R2_0,
Expand Down

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