Merge branch 'master' of https://github.com/aquynh/capstone

fourks · May 7, 2017 · 7ca24f1 · 7ca24f1
2 parents ce8a822 + a8ad69a
commit 7ca24f1
Show file tree

Hide file tree

Showing 5 changed files with 21 additions and 6 deletions.
diff --git a/Makefile b/Makefile
@@ -397,7 +397,7 @@ uninstall:
 
 clean:
 	rm -f $(LIBOBJ)
-	rm -f $(BLDIR)/lib$(LIBNAME).* $(BLDIR)/$(LIBNAME).*
+	rm -f $(BLDIR)/lib$(LIBNAME).* $(BLDIR)/$(LIBNAME).pc
 	rm -f $(PKGCFGF)
 	$(MAKE) -C cstool clean
 

diff --git a/arch/ARM/ARMInstPrinter.c b/arch/ARM/ARMInstPrinter.c
@@ -588,6 +588,11 @@ void ARM_printInst(MCInst *MI, SStream *O, void *Info)
 									MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
 									MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, 0));
 									MI->flat_insn->detail->arm.op_count++;
+                                    // this instruction implicitly read/write SP register
+                                    MI->flat_insn->detail->regs_read[MI->flat_insn->detail->regs_read_count] = ARM_REG_SP;
+                                    MI->flat_insn->detail->regs_read_count++;
+                                    MI->flat_insn->detail->regs_write[MI->flat_insn->detail->regs_write_count] = ARM_REG_SP;
+                                    MI->flat_insn->detail->regs_write_count++;
 								}
 								SStream_concat0(O, "}");
 								return;

diff --git a/arch/X86/X86ATTInstPrinter.c b/arch/X86/X86ATTInstPrinter.c
@@ -676,7 +676,7 @@ static void printMemReference(MCInst *MI, unsigned Op, SStream *O)
 	MCOperand *DispSpec = MCInst_getOperand(MI, Op + X86_AddrDisp);
 	MCOperand *SegReg = MCInst_getOperand(MI, Op + X86_AddrSegmentReg);
 	uint64_t ScaleVal;
-	int reg;
+	int segreg;
 
 	if (MI->csh->detail) {
 		MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM;
@@ -689,11 +689,11 @@ static void printMemReference(MCInst *MI, unsigned Op, SStream *O)
 	}
 
 	// If this has a segment register, print it.
-	reg = MCOperand_getReg(SegReg);
-	if (reg) {
+	segreg = MCOperand_getReg(SegReg);
+	if (segreg) {
 		_printOperand(MI, Op + X86_AddrSegmentReg, O);
 		if (MI->csh->detail) {
-			MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = reg;
+			MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = segreg;
 		}
 
 		SStream_concat0(O, ":");
@@ -728,7 +728,8 @@ static void printMemReference(MCInst *MI, unsigned Op, SStream *O)
 				}
 			}
 		} else {
-			//SStream_concat0(O, "0");
+			if (segreg)
+				SStream_concat0(O, "0");
 		}
 	}
 

diff --git a/arch/X86/X86Disassembler.c b/arch/X86/X86Disassembler.c
@@ -835,6 +835,12 @@ bool X86_getInstruction(csh ud, const uint8_t *code, size_t code_len,
 
 		result = (!translateInstruction(instr, &insn)) ?  true : false;
 		if (result) {
+			// quick fix for #904. TODO: fix this properly in the next update
+			if (handle->mode & CS_MODE_64 &&
+				(instr->Opcode == X86_LES16rm || instr->Opcode == X86_LES32rm))
+				// LES is invalid in x64
+				return false;
+
 			instr->imm_size = insn.immSize;
 			if (handle->detail) {
 				update_pub_insn(instr->flat_insn, &insn, instr->x86_prefix);

diff --git a/arch/X86/X86DisassemblerDecoder.c b/arch/X86/X86DisassemblerDecoder.c
@@ -2133,6 +2133,9 @@ static bool checkPrefix(struct InternalInstruction *insn)
 				// invalid LOCK
 				return true;
 
+			// nop dword [rax]
+			case X86_NOOPL:
+
 			// DEC
 			case X86_DEC16m:
 			case X86_DEC32m: