VHDL 2008/93/87 simulator

🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

VUnit is a unit testing framework for VHDL/SystemVerilog

UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improv…

Reverse engineered SystemVerilog RTL version of the Yamaha OPL3 (YMF262) FM Synthesizer

A huge VHDL library for FPGA development

A collection of reusable, high-quality, peer-reviewed VHDL building blocks.

VHDL description of 6502 processor with FPGA synthesis support.