franhervas99
Follow
Starred repositories
A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
A comprehensive roadmap for aspiring Embedded Systems Engineers, featuring a curated list of learning resources.
UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improv…
VUnit is a unit testing framework for VHDL/SystemVerilog
Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
A customizable hardware prefetching framework using online reinforcement learning as described in the MICRO 2021 paper by Bera et al. (https://arxiv.org/pdf/2109.12021.pdf).
Driver for SSD1306, SSD1331, SSD1351, IL9163, ILI9341, ST7735, PCD8544, Nokia 5110 displays running on Arduino/ESP32/Linux (Rasperry) platforms
VHDL description of 6502 processor with FPGA synthesis support.
AXI4 and AXI4-Lite interface definitions
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
training labs and examples
🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
microcontroller-based FPGA / JTAG programmer
Examples of using cocotb for functional verification of VHDL designs with GHDL.
Repository to show an example of how to do version control with Vivado and Xilinx SDK
A Simple FPGA Core for Creating VGA/DVI/HDMI/OpenLDI Signals
Reverse engineered SystemVerilog RTL version of the Yamaha OPL3 (YMF262) FM Synthesizer
Python/C/RTL cosimulation with Xilinx's xsim simulator
A curated list of modern Generative Artificial Intelligence projects and services
A HARDWARE IMPLEMENTATION OF ARTIFICIAL NEURAL NETWORKS FOR INFERENCE
