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# Copyright (c) Fredrik Andersson, 2023 | ||
# All rights reserved | ||
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""" | ||
Example with synthesis of a verilog file, then creation of a yosys | ||
component from the synthesized netlist. | ||
The verilog file describes a fibonacci sequence generator | ||
The example will generate a gtkwave file, 'fibonacci.vcd'. | ||
""" | ||
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import os | ||
import sys | ||
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from digsim.circuit import Circuit | ||
from digsim.circuit.components import Clock, PushButton, YosysComponent | ||
from digsim.synth import Synthesis | ||
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# Do verilog synthesis with Yosys (with helper python class) | ||
# Input file fibonacci.v will generate fibonacci.json | ||
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input_verilog_file = f"{os.path.dirname(__file__)}/fibonacci.v" | ||
yosys_output_file = f"{os.path.dirname(__file__)}/fibonacci.json" | ||
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print(f"Start synthesis of '{input_verilog_file}'") | ||
synthesis = Synthesis(input_verilog_file, yosys_output_file, "fibonacci") | ||
if not synthesis.execute(silent=True): | ||
# print log and exit if error occurs | ||
print("\n======== Yosys Log ========") | ||
log = synthesis.get_log() | ||
for line in log: | ||
print(f"YOSYS {line}") | ||
print("======== Yosys Log ========\n") | ||
sys.exit(1) | ||
print("Synthesis done!") | ||
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# Create circuit for simulation | ||
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circuit = Circuit(vcd="fibonacci.vcd") | ||
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# Create components in circuit, Clock, Reset button and Yosys component (fibonacci) | ||
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clk = Clock(circuit, "clk", frequency=1000) | ||
reset = PushButton(circuit, "reset") | ||
synth_component = YosysComponent(circuit, path=yosys_output_file) | ||
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# Connect clock and reset button to synth_component (fibonacci) | ||
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clk.O.wire = synth_component.clk | ||
reset.O.wire = synth_component.reset | ||
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# Initialize circuit | ||
circuit.init() | ||
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# Push reset button and run the simulation for 1ms | ||
reset.push() | ||
circuit.run(ms=1) | ||
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print("\n===================== Reset ==========================\n") | ||
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# Print component info | ||
print(synth_component) | ||
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print("\n===================== Start ==========================\n") | ||
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# Release reset button and run the simulation for 1us | ||
reset.release() | ||
circuit.run(us=1) | ||
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# Run simulation in 16ms (in steps of 1ms, print the index and value each loop) | ||
for _ in range(0, 16): | ||
index = synth_component.index.value | ||
value = synth_component.value.value | ||
print(f"Fibonacci sequence [{index}] value is {value}") | ||
circuit.run(ms=1) |
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module fibonacci(clk, reset, index, value); | ||
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input clk, reset; | ||
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output reg [15:0] index; | ||
output [15:0] value; | ||
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reg [15:0] first; | ||
reg [15:0] next; | ||
wire [15:0] sum; | ||
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always_comb | ||
sum <= first + next; | ||
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always_comb | ||
value <= first; | ||
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always @(posedge clk or posedge reset) | ||
begin | ||
next <= sum; | ||
first <= next; | ||
index <= index + 1; | ||
if (reset) | ||
begin | ||
index <= 0; | ||
first <= 0; | ||
next <= 1; | ||
end | ||
end | ||
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endmodule |
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