Improve error handling for yosys component

CHANGELOG.md

@@ -2,6 +2,7 @@
 
 ## vx.x.x
  * Fix bug when detecting number of modules with yosys 0.9
+ * Improve error handling for yosys component
 
 ## v0.0.1 - First Release
  * Simulation of a digital circuit using a python

src/digsim/app/gui_objects/_yosys_object.py

@@ -5,6 +5,8 @@
 
 from PySide6.QtGui import QAction
 
+from digsim.circuit.components.atoms import DigsimException
+
 from ._image_objects import ImageObject
 
 
@@ -23,5 +25,8 @@ def add_context_menu_action(self, menu, parent):
         reloadAction.triggered.connect(self._reload)
 
     def _reload(self):
-        self.component.reload_file()
+        try:
+            self.component.reload_file()
+        except DigsimException as exc:
+            self._app_model.sig_warning_log.emit("Reload Yosys Warning", str(exc))
         self._app_model.model_reset()

src/digsim/circuit/components/_yosys_component.py

@@ -171,8 +171,8 @@ def _synth_verilog(self):
         with tempfile.NamedTemporaryFile(delete=False) as tmp_file:
             filename = tmp_file.name
         synthesis = Synthesis(self._path, filename, toplevel)
-        if not synthesis.execute():
-            raise YosysComponentException("Yosys synthesis error")
+        if not synthesis.execute(silent=True):
+            raise YosysComponentException(f"Yosys synthesis error {self._path}")
         return filename
 
     def _load_netlist_dict(self):

src/digsim/synth/__init__.py

@@ -3,4 +3,4 @@
 
 """ All classes within digsim.synth namespace """
 
-from ._synthesis import Synthesis  # noqa: F401
+from ._synthesis import Synthesis, SynthesisException  # noqa: F401

src/digsim/synth/_synthesis.py

@@ -7,8 +7,10 @@
 import tempfile
 from pathlib import Path
 
+from digsim.circuit.components.atoms import DigsimException
 
-class SynthesisException(Exception):
+
+class SynthesisException(DigsimException):
     """Exception class for yosys synthesis"""
 
 
@@ -52,7 +54,12 @@ def list_modules(cls, verilog_files):
             success = process.returncode == 0
         Path(script_file).unlink()
         if not success:
-            raise SynthesisException("Yosys execution failed...")
+            files_str = ""
+            for verilog_file in verilog_files:
+                if len(files_str) > 0:
+                    files_str += ", "
+                files_str += Path(verilog_file).name
+            raise SynthesisException(f"Yosys error for {files_str}")
         return modules
 
     def __init__(self, verilog_files, json_output_file, verilog_top_module):