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cmd/compile, runtime: use R20, R21 in ARM64's Duff's devices
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Currently we use R16 and R17 for ARM64's Duff's devices.
According to ARM64 ABI, R16 and R17 can be used by the (external)
linker as scratch registers in trampolines. So don't use these
registers to pass information across functions.

It seems unlikely that calling Duff's devices would need a
trampoline in normal cases. But it could happen if the call
target is out of the 128 MB direct jump limit.

The choice of R20 and R21 is kind of arbitrary. The register
allocator allocates from low-numbered registers. High numbered
registers are chosen so it is unlikely to hold a live value and
forces a spill.

Fixes golang#32773.

Change-Id: Id22d555b5afeadd4efcf62797d1580d641c39218
Reviewed-on: https://go-review.googlesource.com/c/go/+/183842
Run-TryBot: Cherry Zhang <[email protected]>
Reviewed-by: Keith Randall <[email protected]>
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cherrymui committed Jun 26, 2019
1 parent 24f7d89 commit 4ea7aa7
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Showing 7 changed files with 220 additions and 220 deletions.
6 changes: 3 additions & 3 deletions src/cmd/compile/internal/arm64/ggen.go
Original file line number Diff line number Diff line change
Expand Up @@ -36,9 +36,9 @@ func zerorange(pp *gc.Progs, p *obj.Prog, off, cnt int64, _ *uint32) *obj.Prog {
off += int64(gc.Widthptr)
cnt -= int64(gc.Widthptr)
}
p = pp.Appendpp(p, arm64.AMOVD, obj.TYPE_REG, arm64.REGSP, 0, obj.TYPE_REG, arm64.REGRT1, 0)
p = pp.Appendpp(p, arm64.AADD, obj.TYPE_CONST, 0, 8+off, obj.TYPE_REG, arm64.REGRT1, 0)
p.Reg = arm64.REGRT1
p = pp.Appendpp(p, arm64.AMOVD, obj.TYPE_REG, arm64.REGSP, 0, obj.TYPE_REG, arm64.REG_R20, 0)
p = pp.Appendpp(p, arm64.AADD, obj.TYPE_CONST, 0, 8+off, obj.TYPE_REG, arm64.REG_R20, 0)
p.Reg = arm64.REG_R20
p = pp.Appendpp(p, obj.ADUFFZERO, obj.TYPE_NONE, 0, 0, obj.TYPE_MEM, 0, 0)
p.To.Name = obj.NAME_EXTERN
p.To.Sym = gc.Duffzero
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2 changes: 1 addition & 1 deletion src/cmd/compile/internal/arm64/ssa.go
Original file line number Diff line number Diff line change
Expand Up @@ -820,7 +820,7 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
p.To.Type = obj.TYPE_REG
p.To.Reg = v.Reg()
case ssa.OpARM64DUFFZERO:
// runtime.duffzero expects start address in R16
// runtime.duffzero expects start address in R20
p := s.Prog(obj.ADUFFZERO)
p.To.Type = obj.TYPE_MEM
p.To.Name = obj.NAME_EXTERN
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16 changes: 8 additions & 8 deletions src/cmd/compile/internal/ssa/gen/ARM64Ops.go
Original file line number Diff line number Diff line change
Expand Up @@ -495,14 +495,14 @@ func init() {
// arg1 = mem
// auxint = offset into duffzero code to start executing
// returns mem
// R16 aka arm64.REGRT1 changed as side effect
// R20 changed as side effect
{
name: "DUFFZERO",
aux: "Int64",
argLength: 2,
reg: regInfo{
inputs: []regMask{buildReg("R16")},
clobbers: buildReg("R16 R30"),
inputs: []regMask{buildReg("R20")},
clobbers: buildReg("R20 R30"),
},
faultOnNilArg0: true,
},
Expand All @@ -529,19 +529,19 @@ func init() {
},

// duffcopy
// arg0 = address of dst memory (in R17 aka arm64.REGRT2, changed as side effect)
// arg1 = address of src memory (in R16 aka arm64.REGRT1, changed as side effect)
// arg0 = address of dst memory (in R21, changed as side effect)
// arg1 = address of src memory (in R20, changed as side effect)
// arg2 = mem
// auxint = offset into duffcopy code to start executing
// returns mem
// R16, R17 changed as side effect
// R20, R21 changed as side effect
{
name: "DUFFCOPY",
aux: "Int64",
argLength: 3,
reg: regInfo{
inputs: []regMask{buildReg("R17"), buildReg("R16")},
clobbers: buildReg("R16 R17 R26 R30"),
inputs: []regMask{buildReg("R21"), buildReg("R20")},
clobbers: buildReg("R20 R21 R26 R30"),
},
faultOnNilArg0: true,
faultOnNilArg1: true,
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10 changes: 5 additions & 5 deletions src/cmd/compile/internal/ssa/opGen.go

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4 changes: 2 additions & 2 deletions src/cmd/internal/obj/arm64/a.out.go
Original file line number Diff line number Diff line change
Expand Up @@ -241,8 +241,8 @@ const (
// compiler allocates external registers F26 down
const (
REGMIN = REG_R7 // register variables allocated from here to REGMAX
REGRT1 = REG_R16 // ARM64 IP0, for external linker, runtime, duffzero and duffcopy
REGRT2 = REG_R17 // ARM64 IP1, for external linker, runtime, duffcopy
REGRT1 = REG_R16 // ARM64 IP0, external linker may use as a scrach register in trampoline
REGRT2 = REG_R17 // ARM64 IP1, external linker may use as a scrach register in trampoline
REGPR = REG_R18 // ARM64 platform register, unused in the Go toolchain
REGMAX = REG_R25

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