lpc55xx_hic: Reduce CPU clock to 96 MHz due to flash writing constraints

freemanqiu · Jan 13, 2022 · bc3e5a0 · bc3e5a0
1 parent 08d6cb5
commit bc3e5a0
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Showing 4 changed files with 11 additions and 8 deletions.
diff --git a/docs/hic/README.md b/docs/hic/README.md
@@ -8,7 +8,7 @@
 | [kl27z](kl27z.md)             |  M0+ |  48 Mhz |  32 KB | 128 KB |  FS |
 | [lpc11u35](lpc11u35.md)       |  M0  |  48 Mhz |  12 KB |  64 KB |  FS |
 | [lpc4322](lpc4322.md)         |  M4  | 120 MHz | 256 KB | 256 KB |  HS |
-| [lpc55xx](lpc55xx.md)         |  M33 | 150 MHz | 272 KB | 320 KB |  HS |
+| [lpc55xx](lpc55xx.md)         |  M33 |  96 MHz | 272 KB | 320 KB |  HS |
 | [max32625](max32625.md)       |  M4  |  96 MHz | 160 KB | 512 KB |  FS |
 | [nrf52820](nrf52820.md)       |  M4  |  64 MHz |  32 KB | 256 KB |  FS |
 | [sam3u2c](sam3u2c.md)         |  M3  |  96 MHz |  32 KB | 128 KB |  HS |

diff --git a/docs/hic/lpc55xx.md b/docs/hic/lpc55xx.md
@@ -1,7 +1,7 @@
 # lpc55xx HIC
 
 Based on LPC55S69JBD64 chip ([Data Sheet](https://www.nxp.com/docs/en/nxp/data-sheets/LPC55S6x_DS.pdf)):
-- Cortex-M33 150 Mhz (cores)
+- Cortex-M33 96 MHz (2 cores up to 150 Mhz)
 - 640 KB Flash
 - 320 KB RAM
 - High-speed USB 2.0 host/device controller: 8 bi-directional endpoints including EP0 (*)

diff --git a/records/hic_hal/lpc55s69.yaml b/records/hic_hal/lpc55s69.yaml
@@ -7,7 +7,7 @@ common:
         - INTERFACE_LPC55XX
         - CPU_LPC55S69JBD64_cm33_core0
         - DAPLINK_HIC_ID=0x4C504355  # DAPLINK_HIC_ID_LPC55XX
-        - OS_CLOCK=150000000
+        - OS_CLOCK=96000000
     includes:
         - source/hic_hal/nxp/lpc55xx
         - source/hic_hal/nxp/lpc55xx/LPC55S69

diff --git a/source/hic_hal/nxp/lpc55xx/hic_init.c b/source/hic_hal/nxp/lpc55xx/hic_init.c
@@ -172,11 +172,14 @@ void sdk_init(void)
 //! - Configure the USB PHY and USB1 clocks.
 void hic_enable_usb_clocks(void)
 {
-    // For the interface, switch to 150 MHz before enabling USB. The bootloader will stay at 96 MHz
-    // so it can always write internal flash.
-#if defined(DAPLINK_IF)
-    BOARD_BootClockPLL150M();
-#endif
+    // Switching to 150 MHz for interface is disabled because it prevents
+    // interface from writing configuration and updating bootloader.
+    // #if defined(DAPLINK_IF)
+    //     // For the interface, switch to 150 MHz before enabling USB.
+    //     // The bootloader will stay at 96 MHz so it can always write
+    //     // internal flash.
+    //     BOARD_BootClockPLL150M();
+    // #endif
 
     NVIC_ClearPendingIRQ(USB1_IRQn);
     NVIC_ClearPendingIRQ(USB1_NEEDCLK_IRQn);