Merge tag 'u-boot-imx-20191009' of https://gitlab.denx.de/u-boot/cust…

…odians/u-boot-imx u-boot-imx-20191009 ------------------- Travis : https://travis-ci.org/sbabic/u-boot-imx/builds/595148532 - MX6UL / ULZ - Toradex board - Allow to set OCRAM for MX6Q/D - MX7ULP - MX8: (container image, imx8mq_mek), SCU API - fix several board booting from SD/EMMC (cubox-i for example) - pico boards [trini: display5 merged manually] Signed-off-by: Tom Rini <[email protected]>
gameltb · Oct 9, 2019 · eaa0bde · eaa0bde
2 parents 8c05aba + 9fb50c6
commit eaa0bde
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diff --git a/Kconfig b/Kconfig
@@ -256,6 +256,7 @@ config BUILD_TARGET
 				ARCH_SUNXI || RISCV)
 	default "u-boot.kwb" if KIRKWOOD
 	default "u-boot-with-spl.bin" if ARCH_AT91 && SPL_NAND_SUPPORT
+	default "u-boot-with-spl.imx" if ARCH_MX6 && SPL
 	help
 	  Some SoCs need special image types (e.g. U-Boot binary
 	  with a special header) as build targets. By defining

diff --git a/Makefile b/Makefile
@@ -834,10 +834,10 @@ ALL-$(CONFIG_RAMBOOT_PBL) += u-boot.pbl
 endif
 endif
 ALL-$(CONFIG_SPL) += spl/u-boot-spl.bin
-ifeq ($(CONFIG_MX6)$(CONFIG_SECURE_BOOT), yy)
+ifeq ($(CONFIG_MX6)$(CONFIG_IMX_HAB), yy)
 ALL-$(CONFIG_SPL_FRAMEWORK) += u-boot-ivt.img
 else
-ifeq ($(CONFIG_MX7)$(CONFIG_SECURE_BOOT), yy)
+ifeq ($(CONFIG_MX7)$(CONFIG_IMX_HAB), yy)
 ALL-$(CONFIG_SPL_FRAMEWORK) += u-boot-ivt.img
 else
 ALL-$(CONFIG_SPL_FRAMEWORK) += u-boot.img
@@ -1371,9 +1371,17 @@ SPL: spl/u-boot-spl.bin FORCE
 	$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
 
 ifeq ($(CONFIG_ARCH_IMX8M)$(CONFIG_ARCH_IMX8), y)
+ifeq ($(CONFIG_SPL_LOAD_IMX_CONTAINER), y)
+u-boot.cnt: u-boot.bin FORCE
+	$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
+
+flash.bin: spl/u-boot-spl.bin u-boot.cnt FORCE
+	$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
+else
 flash.bin: spl/u-boot-spl.bin u-boot.itb FORCE
 	$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
 endif
+endif
 
 u-boot-with-spl.imx u-boot-with-nand-spl.imx: SPL u-boot.bin FORCE
 	$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
@@ -812,15 +812,15 @@ config ARCH_MX7
 	select ARCH_MISC_INIT
 	select BOARD_EARLY_INIT_F
 	select CPU_V7A
-	select SYS_FSL_HAS_SEC if SECURE_BOOT
+	select SYS_FSL_HAS_SEC if IMX_HAB
 	select SYS_FSL_SEC_COMPAT_4
 	select SYS_FSL_SEC_LE
 	imply MXC_GPIO
 
 config ARCH_MX6
 	bool "Freescale MX6"
 	select CPU_V7A
-	select SYS_FSL_HAS_SEC if SECURE_BOOT
+	select SYS_FSL_HAS_SEC if IMX_HAB
 	select SYS_FSL_SEC_COMPAT_4
 	select SYS_FSL_SEC_LE
 	select SYS_THUMB_BUILD if SPL

diff --git a/arch/arm/cpu/arm926ejs/spear/spl.c b/arch/arm/cpu/arm926ejs/spear/spl.c
@@ -277,7 +277,8 @@ void board_init_f(ulong dummy)
  * BootROM code right after having initialized a few components like the DRAM).
  * The following function is called from SPL common code (board_init_r).
  */
-void board_return_to_bootrom(void)
+int board_return_to_bootrom(struct spl_image_info *spl_image,
+			    struct spl_boot_device *bootdev)
 {
 	/*
 	 * Retrieve the BootROM's stack pointer and jump back to the start of
@@ -294,4 +295,6 @@ void board_return_to_bootrom(void)
 		      "bl back_to_bootrom;"
 #endif
 		      );
+
+	return 0;
 }
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
@@ -552,33 +552,44 @@ dtb-$(CONFIG_MX53) += imx53-cx9020.dtb \
 	imx53-kp.dtb \
 	imx53-m53menlo.dtb
 
-dtb-$(CONFIG_MX6Q) += \
-	imx6-apalis.dtb \
-	imx6q-display5.dtb \
-	imx6q-logicpd.dtb \
-	imx6q-novena.dtb \
-	imx6q-tbs2910.dtb
-
-dtb-$(CONFIG_MX6QDL) += \
+ifneq ($(CONFIG_MX6DL)$(CONFIG_MX6QDL)$(CONFIG_MX6S),)
+dtb-y += \
 	imx6dl-dhcom-pdk2.dtb \
 	imx6dl-icore.dtb \
 	imx6dl-icore-mipi.dtb \
 	imx6dl-icore-rqs.dtb \
 	imx6dl-mamoj.dtb \
+	imx6dl-nitrogen6x.dtb \
+	imx6dl-pico.dtb \
 	imx6dl-sabreauto.dtb \
 	imx6dl-sabresd.dtb \
 	imx6dl-wandboard-revb1.dtb \
+
+endif
+
+ifneq ($(CONFIG_MX6Q)$(CONFIG_MX6QDL),)
+dtb-y += \
+	imx6-apalis.dtb \
 	imx6q-cm-fx6.dtb \
 	imx6q-dhcom-pdk2.dtb \
+	imx6q-display5.dtb \
 	imx6q-icore.dtb \
 	imx6q-icore-mipi.dtb \
 	imx6q-icore-rqs.dtb \
+	imx6q-logicpd.dtb \
+	imx6q-nitrogen6x.dtb \
+	imx6q-novena.dtb \
+	imx6q-pico.dtb \
 	imx6q-sabreauto.dtb \
+	imx6q-sabrelite.dtb \
 	imx6q-sabresd.dtb \
+	imx6q-tbs2910.dtb \
 	imx6q-wandboard-revb1.dtb \
 	imx6qp-sabreauto.dtb \
 	imx6qp-sabresd.dtb \
-	imx6qp-wandboard-revd1.dtb
+	imx6qp-wandboard-revd1.dtb \
+
+endif
 
 dtb-$(CONFIG_MX6SL) += imx6sl-evk.dtb
 
@@ -606,7 +617,8 @@ dtb-$(CONFIG_MX6ULL) += \
 	imx6ull-14x14-evk.dtb \
 	imx6ull-colibri.dtb \
 	imx6ull-phycore-segin.dtb \
-	imx6ull-dart-6ul.dtb
+	imx6ull-dart-6ul.dtb \
+	imx6ulz-14x14-evk.dtb
 
 dtb-$(CONFIG_ARCH_MX6) += \
 	imx6-apalis.dtb \
@@ -629,7 +641,8 @@ dtb-$(CONFIG_ARCH_IMX8) += \
 	fsl-imx8qxp-colibri.dtb \
 	fsl-imx8qxp-mek.dtb
 
-dtb-$(CONFIG_ARCH_IMX8M) += fsl-imx8mq-evk.dtb
+dtb-$(CONFIG_ARCH_IMX8M) += fsl-imx8mq-evk.dtb \
+	imx8mm-evk.dtb
 
 dtb-$(CONFIG_RCAR_GEN2) += \
 	r8a7790-lager-u-boot.dtb \

diff --git a/arch/arm/dts/fsl-imx8mq.dtsi b/arch/arm/dts/fsl-imx8mq.dtsi
@@ -19,6 +19,8 @@
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/pinctrl/pins-imx8mq.h>
+#include <dt-bindings/reset/imx8mq-reset.h>
+#include <dt-bindings/power/imx8mq-power.h>
 #include <dt-bindings/thermal/thermal.h>
 
 / {
@@ -71,12 +73,6 @@
 		interrupt-parent = <&gic>;
 	};
 
-	power: power-controller {
-		compatible = "fsl,imx8mq-pm-domain";
-		num-domains = <11>;
-		#power-domain-cells = <1>;
-	};
-
 	pwm2: pwm@30670000 {
 		compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
 		reg = <0x0 0x30670000 0x0 0x10000>;
@@ -269,13 +265,50 @@
 		#clock-cells = <1>;
 	};
 
+	src: reset-controller@30390000 {
+		compatible = "fsl,imx8mq-src", "syscon";
+		reg = <0x0 0x30390000 0x0 0x10000>;
+		#reset-cells = <1>;
+	};
+
 	gpc: gpc@303a0000 {
 		compatible = "fsl,imx8mq-gpc", "fsl,imx7d-gpc", "syscon";
 		reg = <0x0 0x303a0000 0x0 0x10000>;
 		interrupt-controller;
 		interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 		#interrupt-cells = <3>;
 		interrupt-parent = <&gic>;
+
+		pgc {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			/*
+			 * As per comment in ATF source code:
+			 *
+			 * PCIE1 and PCIE2 share the
+			 * same reset signal, if we
+			 * power down PCIE2, PCIE1
+			 * will be held in reset too.
+			 *
+			 * So instead of creating two
+			 * separate power domains for
+			 * PCIE1 and PCIE2 we create a
+			 * link between both and use
+			 * it as a shared PCIE power
+			 * domain.
+			 */
+			pgc_pcie: power-domain@1 {
+				#power-domain-cells = <0>;
+				reg = <IMX8M_POWER_DOMAIN_PCIE1>;
+				power-domains = <&pgc_pcie2>;
+			};
+
+			pgc_pcie2: power-domain@a {
+				#power-domain-cells = <0>;
+				reg = <IMX8M_POWER_DOMAIN_PCIE2>;
+			};
+		};
 	};
 
 	usdhc1: usdhc@30b40000 {

diff --git a/arch/arm/dts/fsl-imx8qm.dtsi b/arch/arm/dts/fsl-imx8qm.dtsi
@@ -21,6 +21,13 @@
 	aliases {
 		ethernet0 = &fec1;
 		ethernet1 = &fec2;
+		gpio0 = &gpio1;
+		gpio1 = &gpio2;
+		gpio2 = &gpio3;
+		gpio3 = &gpio4;
+		gpio4 = &gpio5;
+		gpio5 = &gpio6;
+		gpio6 = &gpio7;
 		serial0 = &lpuart0;
 		serial1 = &lpuart1;
 		serial2 = &lpuart2;

diff --git a/arch/arm/dts/imx28-u-boot.dtsi b/arch/arm/dts/imx28-u-boot.dtsi
@@ -5,7 +5,6 @@
  *
  * SPDX-License-Identifier:     GPL-2.0+ or X11
  */
-#include "imx28.dtsi"
 
 &gpio0 {
 	gpio-ranges = <&pinctrl 0 0 29>;

diff --git a/arch/arm/dts/imx6dl-nitrogen6x.dts b/arch/arm/dts/imx6dl-nitrogen6x.dts
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// Copyright 2013-2019 Boundary Devices, Inc.
+// Copyright 2012 Freescale Semiconductor, Inc.
+// Copyright 2011 Linaro Ltd.
+
+/dts-v1/;
+
+#include "imx6dl.dtsi"
+#include "imx6qdl-nitrogen6x.dtsi"
+
+/ {
+	model = "Boundary Devices i.MX6 DualLite Nitrogen6x Board";
+	compatible = "boundary,imx6dl-nitrogen6x", "fsl,imx6dl";
+};
diff --git a/arch/arm/dts/imx6dl-pico.dts b/arch/arm/dts/imx6dl-pico.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright 2018 Technexion Ltd.
+//
+// Author: Wig Cheng <[email protected]>
+//	   Richard Hu <[email protected]>
+//	   Tapani Utriainen <[email protected]>
+
+/dts-v1/;
+
+#include "imx6dl.dtsi"
+#include "imx6qdl-pico.dtsi"
+
+/ {
+	model = "TechNexion PICO-IMX6 DualLite/Solo";
+	compatible = "technexion,imx6dl-pico", "fsl,imx6dl";
+};
diff --git a/arch/arm/dts/imx6q-display5-u-boot.dtsi b/arch/arm/dts/imx6q-display5-u-boot.dtsi
@@ -31,6 +31,11 @@
 	chosen {
 		stdout-path = &uart5;
 	};
+
+	wdt-reboot {
+		compatible = "wdt-reboot";
+		wdt = <&wdog1>;
+	};
 };
 
 &i2c3 {

diff --git a/arch/arm/dts/imx6q-nitrogen6x.dts b/arch/arm/dts/imx6q-nitrogen6x.dts
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// Copyright 2013-2019 Boundary Devices, Inc.
+// Copyright 2012 Freescale Semiconductor, Inc.
+// Copyright 2011 Linaro Ltd.
+
+/dts-v1/;
+
+#include "imx6q.dtsi"
+#include "imx6qdl-nitrogen6x.dtsi"
+
+/ {
+	model = "Boundary Devices i.MX6 Quad Nitrogen6x Board";
+	compatible = "boundary,imx6q-nitrogen6x", "fsl,imx6q";
+};
+
+&sata {
+	status = "okay";
+};
diff --git a/arch/arm/dts/imx6q-pico.dts b/arch/arm/dts/imx6q-pico.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright 2018 Technexion Ltd.
+//
+// Author: Wig Cheng <[email protected]>
+//	   Richard Hu <[email protected]>
+//	   Tapani Utriainen <[email protected]>
+
+/dts-v1/;
+
+#include "imx6q.dtsi"
+#include "imx6qdl-pico.dtsi"
+
+/ {
+	model = "TechNexion PICO-IMX6 Quad";
+	compatible = "technexion,imx6q-pico", "fsl,imx6q";
+};
diff --git a/arch/arm/dts/imx6q-sabrelite.dts b/arch/arm/dts/imx6q-sabrelite.dts
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// Copyright 2013-2019 Boundary Devices, Inc.
+// Copyright 2012 Freescale Semiconductor, Inc.
+// Copyright 2011 Linaro Ltd.
+
+/dts-v1/;
+
+#include "imx6q.dtsi"
+#include "imx6qdl-sabrelite.dtsi"
+
+/ {
+	model = "Freescale i.MX6 Quad SABRE Lite Board";
+	compatible = "fsl,imx6q-sabrelite", "fsl,imx6q";
+};
+
+&sata {
+	status = "okay";
+};