This project verifies an AHB-APB bridge using SystemVerilog UVM, ensuring correct protocol conversion, synchronization, and data integrity.

MLPerf™ Tiny is an ML benchmark suite for extremely low-power systems such as microcontrollers

Ubuntu 22.04 (Desktop) Boot Image (U-boot, Linux Kernel, Ubuntu RootFS) for Zynq MPSoC.

Everything you need to build state-of-the-art foundation models, end-to-end.

PIDray dataset detection using YoloV8 (compared with YoloV5)

A thread safe simple C++ wrapper for FFTW & MKL

Rocket Chip Generator

Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

New HPC documentation using material for mkdocs

Want a faster ML processor? Do it yourself! -- A framework for playing with custom opcodes to accelerate TensorFlow Lite for Microcontrollers (TFLM). . . . . . Online tutorial: https://google.githu…

Deep and online learning with spiking neural networks in Python

An LSTM template and a few examples using Vivado HLS

A General-purpose Task-parallel Programming System using Modern C++

For the full documentation, see https://efc-package.readthedocs.io/en/latest/

Towards Mitigating Flush-based Cache Attacks via Collaborating Flush Instructions and Timers on ARMv8-A

This repository includes the code for Prodigy: Towards Unsupervised Anomaly Detection in Production HPC Systems

A translator from Intel SSE intrinsics to Arm/Aarch64 NEON implementation

Microarchitectural exploitation and other hardware attacks.

Next-gen Rowhammer fuzzer that uses non-uniform, frequency-based patterns (IEEE S&P '22).

Variant 1 of the Spectre attack which is to bypass the bounds checks in the target process and retrieve the private data. Here in this example, I have demonstrated how to retrieve a string data usi…

log anomaly detection toolkit including DeepLog

PyTorch implementation of Deeplog: Anomaly detection and diagnosis from system logs through deep learning

This repository contains examples of Flush+Flush cache attacks

Tracking interesting Linux (and UNIX) malware. Send PRs

Leaked Mirai Source Code for Research/IoC Development Purposes

Proof-of-concept implementation for the paper "A Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUs" (IEEE S&P 2023)