Merge branch 'master' of git://git.denx.de/u-boot-arm

Makefile

@@ -609,6 +609,8 @@ KBUILD_CFLAGS += $(KCFLAGS)
 UBOOTINCLUDE    := \
 		-Iinclude \
 		$(if $(KBUILD_SRC), -I$(srctree)/include) \
+		$(if $(CONFIG_SYS_THUMB_BUILD), $(if $(CONFIG_HAS_THUMB2),, \
+			-I$(srctree)/arch/$(ARCH)/thumb1/include),) \
 		-I$(srctree)/arch/$(ARCH)/include \
 		-include $(srctree)/include/linux/kconfig.h
 

arch/arm/Kconfig

@@ -10,6 +10,9 @@ config ARM64
 config HAS_VBAR
         bool
 
+config HAS_THUMB2
+        bool
+
 config CPU_ARM720T
         bool
 
@@ -32,9 +35,11 @@ config CPU_ARM1176
 config CPU_V7
         bool
         select HAS_VBAR
+        select HAS_THUMB2
 
 config CPU_V7M
 	bool
+        select HAS_THUMB2
 
 config CPU_PXA
         bool

arch/arm/cpu/arm926ejs/Makefile

@@ -20,3 +20,14 @@ obj-$(CONFIG_MX25) += mx25/
 obj-$(CONFIG_MX27) += mx27/
 obj-$(if $(filter mxs,$(SOC)),y) += mxs/
 obj-$(if $(filter spear,$(SOC)),y) += spear/
+
+# some files can only build in ARM or THUMB2, not THUMB1
+
+ifdef CONFIG_SYS_THUMB_BUILD
+ifndef CONFIG_HAS_THUMB2
+
+CFLAGS_cpu.o := -marm
+CFLAGS_cache.o := -marm
+
+endif
+endif

arch/arm/cpu/arm926ejs/cache.c

@@ -82,4 +82,9 @@ void flush_dcache_all(void)
 /*
  * Stub implementations for l2 cache operations
  */
+
 __weak void l2_cache_disable(void) {}
+
+#if defined CONFIG_SYS_THUMB_BUILD
+__weak void invalidate_l2_cache(void) {}
+#endif

arch/arm/cpu/armv7m/stm32f4/flash.c

@@ -97,6 +97,9 @@ int flash_erase(flash_info_t *info, int first, int last)
 		while (readl(&STM32_FLASH->sr) & STM32_FLASH_SR_BSY)
 			;
 
+		/* clear old sector number before writing a new one */
+		clrbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_SNB_MASK);
+
 		if (bank == 0) {
 			setbits_le32(&STM32_FLASH->cr,
 				     (i << STM32_FLASH_CR_SNB_OFFSET));
@@ -114,9 +117,9 @@ int flash_erase(flash_info_t *info, int first, int last)
 			;
 
 		clrbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_SER);
-		stm32f4_flash_lock(1);
 	}
 
+	stm32f4_flash_lock(1);
 	return 0;
 }
 

arch/arm/cpu/armv8/cache_v8.c

@@ -32,7 +32,7 @@ inline void set_pgtable_table(u64 *page_table, u64 index, u64 *table_addr)
 }
 
 /* to activate the MMU we need to set up virtual memory */
-static void mmu_setup(void)
+__weak void mmu_setup(void)
 {
 	bd_t *bd = gd->bd;
 	u64 *page_table = (u64 *)gd->arch.tlb_addr, i, j;

arch/arm/include/asm/arch-stm32f4/stm32.h

@@ -104,6 +104,7 @@ struct stm32_flash_regs {
 #define STM32_FLASH_CR_STRT		(1 << 16)
 #define STM32_FLASH_CR_LOCK		(1 << 31)
 #define STM32_FLASH_CR_SNB_OFFSET	3
+#define STM32_FLASH_CR_SNB_MASK		(15 << STM32_FLASH_CR_SNB_OFFSET)
 
 enum clock {
 	CLOCK_CORE,

arch/arm/include/asm/cache.h

@@ -16,6 +16,9 @@
 /*
  * Invalidate L2 Cache using co-proc instruction
  */
+#ifdef CONFIG_SYS_THUMB_BUILD
+void invalidate_l2_cache(void);
+#else
 static inline void invalidate_l2_cache(void)
 {
 	unsigned int val=0;
@@ -24,6 +27,7 @@ static inline void invalidate_l2_cache(void)
 		: : "r" (val) : "cc");
 	isb();
 }
+#endif
 
 void l2_cache_enable(void);
 void l2_cache_disable(void);

arch/arm/include/asm/system.h

@@ -17,6 +17,7 @@
 #define PGTABLE_SIZE	(0x10000)
 /* 2MB granularity */
 #define MMU_SECTION_SHIFT	21
+#define MMU_SECTION_SIZE	(1 << MMU_SECTION_SHIFT)
 
 #ifndef __ASSEMBLY__
 
@@ -278,11 +279,6 @@ enum {
  */
 void mmu_page_table_flush(unsigned long start, unsigned long stop);
 
-#ifdef CONFIG_SYS_NONCACHED_MEMORY
-void noncached_init(void);
-phys_addr_t noncached_alloc(size_t size, size_t align);
-#endif /* CONFIG_SYS_NONCACHED_MEMORY */
-
 #endif /* __ASSEMBLY__ */
 
 #define arch_align_stack(x) (x)
@@ -302,6 +298,11 @@ phys_addr_t noncached_alloc(size_t size, size_t align);
 void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
 				     enum dcache_option option);
 
+#ifdef CONFIG_SYS_NONCACHED_MEMORY
+void noncached_init(void);
+phys_addr_t noncached_alloc(size_t size, size_t align);
+#endif /* CONFIG_SYS_NONCACHED_MEMORY */
+
 #endif /* __ASSEMBLY__ */
 
 #endif

arch/arm/lib/Makefile

@@ -60,3 +60,27 @@ obj-$(CONFIG_DEBUG_LL)	+= debug.o
 ifneq (,$(findstring -mabi=aapcs-linux,$(PLATFORM_CPPFLAGS)))
 extra-y	+= eabi_compat.o
 endif
+
+# some files can only build in ARM or THUMB2, not THUMB1
+
+ifdef CONFIG_SYS_THUMB_BUILD
+ifndef CONFIG_HAS_THUMB2
+
+# for C files, just apend -marm, which will override previous -mthumb*
+
+CFLAGS_cache.o := -marm
+CFLAGS_cache-cp15.o := -marm
+
+# For .S, drop -mthumb* and other thumb-related options.
+# CFLAGS_REMOVE_* would not have an effet, so AFLAGS_REMOVE_*
+# was implemented and is used here.
+# Also, define ${target}_NO_THUMB_BUILD for these two targets
+# so that the code knows it should not use Thumb.
+
+AFLAGS_REMOVE_memset.o := -mthumb -mthumb-interwork
+AFLAGS_REMOVE_memcpy.o := -mthumb -mthumb-interwork
+AFLAGS_memset.o := -DMEMSET_NO_THUMB_BUILD
+AFLAGS_memcpy.o := -DMEMCPY_NO_THUMB_BUILD
+
+endif
+endif

arch/arm/lib/cache.c

@@ -88,3 +88,14 @@ phys_addr_t noncached_alloc(size_t size, size_t align)
 	return next;
 }
 #endif /* CONFIG_SYS_NONCACHED_MEMORY */
+
+#if defined(CONFIG_SYS_THUMB_BUILD)
+void invalidate_l2_cache(void)
+{
+	unsigned int val = 0;
+
+	asm volatile("mcr p15, 1, %0, c15, c11, 0 @ invl l2 cache"
+		: : "r" (val) : "cc");
+	isb();
+}
+#endif

arch/arm/lib/memcpy.S

@@ -13,7 +13,7 @@
 #include <linux/linkage.h>
 #include <asm/assembler.h>
 
-#ifdef CONFIG_SYS_THUMB_BUILD
+#if defined(CONFIG_SYS_THUMB_BUILD) && !defined(MEMCPY_NO_THUMB_BUILD)
 #define W(instr)	instr.w
 #else
 #define W(instr)	instr
@@ -62,7 +62,7 @@
 
 /* Prototype: void *memcpy(void *dest, const void *src, size_t n); */
 	.syntax unified
-#ifdef CONFIG_SYS_THUMB_BUILD
+#if defined(CONFIG_SYS_THUMB_BUILD) && !defined(MEMCPY_NO_THUMB_BUILD)
 	.thumb
 	.thumb_func
 #endif

arch/arm/lib/memset.S

@@ -16,7 +16,7 @@
 	.align	5
 
 	.syntax unified
-#ifdef CONFIG_SYS_THUMB_BUILD
+#if defined(CONFIG_SYS_THUMB_BUILD) && !defined(MEMSET_NO_THUMB_BUILD)
 	.thumb
 	.thumb_func
 #endif

arch/arm/lib/semihosting.c

@@ -31,6 +31,8 @@ static noinline long smh_trap(unsigned int sysnum, void *addr)
 	register long result asm("r0");
 #if defined(CONFIG_ARM64)
 	asm volatile ("hlt #0xf000" : "=r" (result) : "0"(sysnum), "r"(addr));
+#elif defined(CONFIG_CPU_V7M)
+	asm volatile ("bkpt #0xAB" : "=r" (result) : "0"(sysnum), "r"(addr));
 #else
 	/* Note - untested placeholder */
 	asm volatile ("svc #0x123456" : "=r" (result) : "0"(sysnum), "r"(addr));
@@ -90,7 +92,7 @@ static long smh_read(long fd, void *memp, size_t len)
 		size_t len;
 	} read;
 
-	debug("%s: fd %ld, memp %p, len %lu\n", __func__, fd, memp, len);
+	debug("%s: fd %ld, memp %p, len %zu\n", __func__, fd, memp, len);
 
 	read.fd = fd;
 	read.memp = memp;
@@ -104,7 +106,7 @@ static long smh_read(long fd, void *memp, size_t len)
 		 * hard to maintain partial read loops and such, just fail
 		 * with an error message.
 		 */
-		printf("%s: ERROR ret %ld, fd %ld, len %lu memp %p\n",
+		printf("%s: ERROR ret %ld, fd %ld, len %zu memp %p\n",
 		       __func__, ret, fd, len, memp);
 		return -1;
 	}

arch/arm/mach-kirkwood/Kconfig

@@ -4,6 +4,9 @@ choice
 	prompt "Marvell Kirkwood board select"
 	optional
 
+config TARGET_OPENRD
+	bool "Marvell OpenRD Board"
+
 config TARGET_DREAMPLUG
 	bool "DreamPlug Board"
 
@@ -51,6 +54,7 @@ endchoice
 config SYS_SOC
 	default "kirkwood"
 
+source "board/Marvell/openrd/Kconfig"
 source "board/Marvell/dreamplug/Kconfig"
 source "board/Marvell/guruplug/Kconfig"
 source "board/Marvell/sheevaplug/Kconfig"

arch/arm/mach-kirkwood/Makefile

@@ -9,3 +9,9 @@
 obj-y	= cpu.o
 obj-y	+= cache.o
 obj-y	+= mpp.o
+
+# cpu.o and cache.o contain CP15 instructions which cannot be run in
+# Thumb state, so build them for ARM state even with CONFIG_SYS_THUMB_BUILD
+
+CFLAGS_cpu.o := -marm
+CFLAGS_cache.o := -marm

arch/arm/mach-orion5x/Makefile

@@ -16,3 +16,13 @@ obj-y	+= timer.o
 ifndef CONFIG_SKIP_LOWLEVEL_INIT
 obj-y	+= lowlevel_init.o
 endif
+
+# some files can only build in ARM or THUMB2, not THUMB1
+
+ifdef CONFIG_SYS_THUMB_BUILD
+ifndef CONFIG_HAS_THUMB2
+
+CFLAGS_cpu.o := -marm
+
+endif
+endif

arch/arm/mach-tegra/Makefile

@@ -15,6 +15,7 @@ obj-$(CONFIG_CMD_ENTERRCM) += cmd_enterrcm.o
 obj-$(CONFIG_PWM_TEGRA) += pwm.o
 endif
 
+obj-$(CONFIG_ARM64) += arm64-mmu.o
 obj-y += ap.o
 obj-y += board.o board2.o
 obj-y += cache.o