DTS: Fix ETH PHY reset on HSC|DDC boards (imx53)

After the commit: "eth: dm: fec: Add gpio phy reset binding"
SHA1: efd0b79

The FEC ETH driver switched to PHY GPIO reset performed with data defined
in DTS.
For the HSC|DDC boards the GPIO reset signal is active low and hence the
wrong DTS description must be changed (otherwise the reset for ETH is not
properly setup).

Signed-off-by: Lukasz Majewski <[email protected]>

arch/arm/dts/imx53-kp.dts

@@ -23,7 +23,7 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_eth>;
 	phy-mode = "rmii";
-	phy-reset-gpios = <&gpio7 6 0>;
+	phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
 	status = "okay";
 };