Skip to content

Commit

Permalink
Merge tag 'xilinx-for-v2020.01-part2' of https://gitlab.denx.de/u-boo…
Browse files Browse the repository at this point in the history
…t/custodians/u-boot-microblaze

Xilinx/FPGA changes for v2020.01 part 2

common:
- Fix manual relocation for repeatable commands

arm:
- Also clean up generated dtbos

microblaze:
- Add support for Manual relocation in crypto framework
- Tune and align architecture bootm support

zynq:
- DT sync ups
- Some defconfig updates
- Remove empty board_early_init_f()

zynqmp:
- Clean firmware handing via drivers/firmware/
- DT/defconfig name alignments
- DT cleanups with using firmware based clock driver
- Some defconfig updates
- Add IIO ina226 DT description
- Tune zynqmp_psu_init_minimalize.sh script
- Add single nand mini configuration, e-a2197, m-a2197-02/03 and zcu216

versal:
- Clean firmware handing via drivers/firmware/
- Add gpio support
- Enable DT overlay/USB/CLK/FPGA
- DT updates
- Tune mini configuration

spi:
- gqspi - Remove unused headers
  • Loading branch information
trini committed Oct 25, 2019
2 parents 17fd991 + 3ad95ed commit e382713
Show file tree
Hide file tree
Showing 97 changed files with 4,078 additions and 480 deletions.
1 change: 0 additions & 1 deletion arch/arm/Kconfig
Original file line number Diff line number Diff line change
Expand Up @@ -1008,7 +1008,6 @@ config ARCH_VF610

config ARCH_ZYNQ
bool "Xilinx Zynq based platform"
select BOARD_EARLY_INIT_F if WDT
select CLK
select CLK_ZYNQ
select CPU_V7A
Expand Down
12 changes: 8 additions & 4 deletions arch/arm/dts/Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -250,9 +250,12 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
avnet-ultra96-rev1.dtb \
avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dtb \
zynqmp-a2197-revA.dtb \
zynqmp-a2197-g-revA.dtb \
zynqmp-a2197-m-revA.dtb \
zynqmp-a2197-p-revA.dtb \
zynqmp-e-a2197-00-revA.dtb \
zynqmp-g-a2197-00-revA.dtb \
zynqmp-m-a2197-01-revA.dtb \
zynqmp-m-a2197-02-revA.dtb \
zynqmp-m-a2197-03-revA.dtb \
zynqmp-p-a2197-00-revA.dtb \
zynqmp-mini.dtb \
zynqmp-mini-emmc0.dtb \
zynqmp-mini-emmc1.dtb \
Expand All @@ -268,6 +271,7 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
zynqmp-zcu111-revA.dtb \
zynqmp-zcu1275-revA.dtb \
zynqmp-zcu1275-revB.dtb \
zynqmp-zcu216-revA.dtb \
zynqmp-zc1232-revA.dtb \
zynqmp-zc1254-revA.dtb \
zynqmp-zc1751-xm015-dc1.dtb \
Expand Down Expand Up @@ -833,4 +837,4 @@ PHONY += dtbs
dtbs: $(addprefix $(obj)/, $(dtb-y))
@:

clean-files := *.dtb *_HS
clean-files := *.dtb *.dtbo *_HS
2 changes: 1 addition & 1 deletion arch/arm/dts/versal-mini-emmc1.dts
Original file line number Diff line number Diff line change
Expand Up @@ -35,7 +35,7 @@
#size-cells = <0x2>;
ranges;

sdhci1: sdhci@f105000 {
sdhci1: sdhci@f1050000 {
compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a";
status = "okay";
reg = <0x0 0xf1050000 0x0 0x10000>;
Expand Down
27 changes: 27 additions & 0 deletions arch/arm/dts/zynq-7000.dtsi
Original file line number Diff line number Diff line change
Expand Up @@ -213,6 +213,33 @@
#size-cells = <0>;
};

smcc: memory-controller@e000e000 {
#address-cells = <1>;
#size-cells = <1>;
status = "disabled";
clock-names = "memclk", "apb_pclk";
clocks = <&clkc 11>, <&clkc 44>;
compatible = "arm,pl353-smc-r2p1", "arm,primecell";
interrupt-parent = <&intc>;
interrupts = <0 18 4>;
ranges ;
reg = <0xe000e000 0x1000>;
nand0: flash@e1000000 {
status = "disabled";
compatible = "arm,pl353-nand-r2p1";
reg = <0xe1000000 0x1000000>;
#address-cells = <1>;
#size-cells = <1>;
};
nor0: flash@e2000000 {
status = "disabled";
compatible = "cfi-flash";
reg = <0xe2000000 0x2000000>;
#address-cells = <1>;
#size-cells = <1>;
};
};

gem0: ethernet@e000b000 {
compatible = "cdns,zynq-gem", "cdns,gem";
reg = <0xe000b000 0x1000>;
Expand Down
Loading

0 comments on commit e382713

Please sign in to comment.