arm: add initial support for the Phytium Durian Board

This adds platform code and the device tree for the Phytium Durian Board.
The initial support comprises the UART and the PCIE.

Cc: Bin Meng <[email protected]>
Cc: Kever Yang <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Heinrich Schuchardt <[email protected]>

Signed-off-by: Steven Hao <[email protected]>

MAINTAINERS

@@ -481,6 +481,13 @@ S:	Maintained
 T:	git https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze.git
 F:	arch/arm/mach-zynqmp-r5/
 
+ARM PHYTIUM
+M:	liuhao <[email protected]>
+M:	shuyiqi <[email protected]>
+S:	Maintained
+F:	drivers/pci/pcie_phytium.c
+F:	arch/arm/dts/phytium-durian.dts
+
 BINMAN
 M:	Simon Glass <[email protected]>
 S:	Maintained

arch/arm/Kconfig

@@ -1631,6 +1631,13 @@ config ARCH_ASPEED
 	select OF_CONTROL
 	imply CMD_DM
 
+config TARGET_DURIAN
+	bool "Support Phytium Durian Platform"
+	select ARM64
+	help
+	  Support for durian platform.
+	  It has 2GB Sdram, uart and pcie.
+
 endchoice
 
 config ARCH_SUPPORT_TFABOOT
@@ -1830,6 +1837,7 @@ source "board/woodburn/Kconfig"
 source "board/xilinx/Kconfig"
 source "board/xilinx/zynq/Kconfig"
 source "board/xilinx/zynqmp/Kconfig"
+source "board/phytium/durian/Kconfig"
 
 source "arch/arm/Kconfig.debug"
 

arch/arm/dts/Makefile

@@ -834,6 +834,8 @@ dtb-$(CONFIG_TARGET_VEXPRESS_CA5X2) += vexpress-v2p-ca5s.dtb
 dtb-$(CONFIG_TARGET_VEXPRESS_CA9X4) += vexpress-v2p-ca9.dtb
 dtb-$(CONFIG_TARGET_VEXPRESS_CA15_TC2) += vexpress-v2p-ca15_a7.dtb
 
+dtb-$(CONFIG_TARGET_DURIAN) += phytium-durian.dtb
+
 targets += $(dtb-y)
 
 # Add any required device tree compiler flags here

arch/arm/dts/phytium-durian.dts

@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019, Phytium Ltd.
+ * shuyiqi  <[email protected]>
+ */
+
+/dts-v1/;
+
+/ {
+	model = "Phytium Durian";
+	compatible = "phytium,durian";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	pcie-controller@40000000 {
+		compatible = "phytium,pcie-host-1.0";
+		device_type = "pci";
+		#address-cells = <3>;
+		#size-cells = <2>;
+		reg = <0x0 0x40000000 0x0 0x10000000>;
+		bus-range = <0x0 0xff>;
+		ranges = <0x1000000 0x0 0x0 0x0 0x50000000 0x0 0xF00000>,
+		<0x2000000 0x0 0x58000000 0x0 0x58000000 0x0 0x28000000>,
+		<0x43000000 0x10 0x00000000 0x10 0x00000000 0x10  0x00000000>;
+	};
+
+	uart@28001000 {
+		compatible = "arm,pl011";
+		reg = <0x0 0x28001000 0x0 0x1000>;
+		clock = <48000000>;
+	};
+};
+

board/phytium/durian/Kconfig

@@ -0,0 +1,12 @@
+if TARGET_DURIAN
+
+config SYS_BOARD
+	default "durian"
+
+config SYS_VENDOR
+	default "phytium"
+
+config SYS_CONFIG_NAME
+	default "durian"
+
+endif

board/phytium/durian/MAINTAINERS

@@ -0,0 +1,8 @@
+DURIAN BOARD
+M:	liuhao <[email protected]>
+M:	shuyiqi <[email protected]>
+S:	Maintained
+F:	board/phytium/durian/*
+F:	include/configs/durian.h
+F:	configs/durian_defconfig
+

board/phytium/durian/Makefile

@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2019
+# shuyiqi  <[email protected]>
+# liuhao   <[email protected]>
+#
+
+obj-y += durian.o
+

board/phytium/durian/README

@@ -0,0 +1,59 @@
+Here is the step-by-step to boot U-Boot on phytium durian board.
+
+Compile U-Boot
+==============
+  > make durian_defconfig
+  > make
+
+Get the prebuild binary about BPF
+=================================
+  > cd ../
+  > git clone https://github.com/phytium-durian/bpf.git
+
+Package the image
+=================
+  > cd bpf
+  > cp ../u-boot/u-boot.bin ./
+  > ./dopack
+
+  The fip-all.bin is the final image.
+
+Flash the image into the spi nor-flash
+======================================
+  Any spi nor-flash and appropriate tool can be used to flash.
+  For example, we choose the S25FL256 chip that produced from
+  SPANSION company and EZP_XPro V1.2.
+
+Reset the board, you can get U-Boot log message from boot console:
+
+Power on...
+Start pcie setup!
+End pcie setup!
+Start ddr setup!
+End ddr setup!
+Jump to entrypoint: 0x500000
+
+U-Boot 2019.10-00594-g9ccc1b17ea-dirty (Oct 18 2019 - 00:17:09 +0800)
+
+DRAM:  1.9 GiB
+In:    uart@28001000
+Out:   uart@28001000
+Err:   uart@28001000
+scanning bus for devices...
+Target spinup took 0 ms.
+SATA link 1 timeout.
+SATA link 2 timeout.
+SATA link 3 timeout.
+AHCI 0001.0000 32 slots 4 ports 6 Gbps 0xf impl SATA mode
+flags: 64bit ncq led only pmp fbss pio slum part sxs
+  Device 0: (0:0) Vendor: ATA Prod.: ST1000DM010-2EP1 Rev: CC43
+            Type: Hard Disk
+            Capacity: 953869.7 MB = 931.5 GB (1953525168 x 512)
+SATA link 0 timeout.
+SATA link 1 timeout.
+SATA link 2 timeout.
+SATA link 3 timeout.
+AHCI 0001.0000 32 slots 4 ports 6 Gbps 0xf impl SATA mode
+flags: 64bit ncq led only pmp fbss pio slum part sxs
+Hit any key to stop autoboot:  0
+durian#

board/phytium/durian/cpu.h

@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2019
+ * Phytium Technology Ltd <www.phytium.com>
+ * shuyiqi <[email protected]>
+ */
+
+#ifndef _FT_DURIAN_H
+#define _FT_DURIAN_H
+
+/* FLUSH L3 CASHE */
+#define HNF_COUNT           0x8
+#define HNF_PSTATE_REQ      (HNF_BASE + 0x10)
+#define HNF_PSTATE_STAT     (HNF_BASE + 0x18)
+#define HNF_PSTATE_OFF      0x0
+#define HNF_PSTATE_SFONLY   0x1
+#define HNF_PSTATE_HALF     0x2
+#define HNF_PSTATE_FULL     0x3
+#define HNF_STRIDE          0x10000
+#define HNF_BASE            (unsigned long)(0x3A200000)
+
+#endif /* _FT_DURIAN_H */
+

board/phytium/durian/durian.c

@@ -0,0 +1,110 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019
+ * shuyiqi <[email protected]>
+ * liuhao  <[email protected]>
+ */
+
+#include <common.h>
+#include <asm/armv8/mmu.h>
+#include <asm/system.h>
+#include <asm/io.h>
+#include <linux/arm-smccc.h>
+#include <linux/kernel.h>
+#include <scsi.h>
+#include "cpu.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	gd->mem_clk = 0;
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size =  PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
+
+int board_init(void)
+{
+	return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+	struct arm_smccc_res res;
+
+	arm_smccc_smc(0x84000009, 0, 0, 0, 0, 0, 0, 0, &res);
+	debug("reset cpu error, %lx\n", res.a0);
+}
+
+static struct mm_region durian_mem_map[] = {
+	{
+		.virt = 0x0UL,
+		.phys = 0x0UL,
+		.size = 0x80000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+				 PTE_BLOCK_NON_SHARE |
+				 PTE_BLOCK_PXN |
+				 PTE_BLOCK_UXN
+	},
+	{
+		.virt = (u64)PHYS_SDRAM_1,
+		.phys = (u64)PHYS_SDRAM_1,
+		.size = (u64)PHYS_SDRAM_1_SIZE,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+				 PTE_BLOCK_NS |
+				 PTE_BLOCK_INNER_SHARE
+	},
+	{
+		0,
+	}
+};
+
+struct mm_region *mem_map = durian_mem_map;
+
+int print_cpuinfo(void)
+{
+	printf("CPU: Phytium ft2004 %ld MHz\n", gd->cpu_clk);
+	return 0;
+}
+
+int __asm_flush_l3_dcache(void)
+{
+	int i, pstate;
+
+	for (i = 0; i < HNF_COUNT; i++)
+		writeq(HNF_PSTATE_SFONLY, HNF_PSTATE_REQ + i * HNF_STRIDE);
+	for (i = 0; i < HNF_COUNT; i++) {
+		do {
+			pstate = readq(HNF_PSTATE_STAT + i * HNF_STRIDE);
+		} while ((pstate & 0xf) != (HNF_PSTATE_SFONLY << 2));
+	}
+
+	for (i = 0; i < HNF_COUNT; i++)
+		writeq(HNF_PSTATE_FULL, HNF_PSTATE_REQ + i * HNF_STRIDE);
+
+	return 0;
+}
+
+int last_stage_init(void)
+{
+	int ret;
+
+	/* pci e */
+	pci_init();
+	/* scsi scan */
+	ret = scsi_scan(true);
+	if (ret) {
+		printf("scsi scan failed\n");
+		return CMD_RET_FAILURE;
+	}
+	return ret;
+}
+

configs/durian_defconfig

@@ -0,0 +1,33 @@
+CONFIG_ARM=y
+CONFIG_ARM_SMCCC=y
+CONFIG_TARGET_DURIAN=y
+CONFIG_SYS_TEXT_BASE=0x500000
+CONFIG_NR_DRAM_BANKS=1
+# CONFIG_PSCI_RESET is not set
+CONFIG_AHCI=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyAMA0,115200 earlycon=pl011,0x28001000 root=/dev/sda2 rw"
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_LAST_STAGE_INIT=y
+CONFIG_SYS_PROMPT="durian#"
+# CONFIG_CMD_LZMADEC is not set
+# CONFIG_CMD_UNZIP is not set
+CONFIG_CMD_PCI=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="phytium-durian"
+# CONFIG_NET is not set
+CONFIG_DM=y
+CONFIG_SCSI_AHCI=y
+CONFIG_AHCI_PCI=y
+CONFIG_BLK=y
+# CONFIG_MMC is not set
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCI_PHYTIUM=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
+CONFIG_DM_SERIAL=y
+CONFIG_PL01X_SERIAL=y

drivers/pci/Kconfig

@@ -51,6 +51,13 @@ config PCIE_ECAM_GENERIC
 	  Say Y here if you want to enable support for generic ECAM-based
 	  PCIe host controllers, such as the one emulated by QEMU.
 
+config PCI_PHYTIUM
+	bool "Phytium PCIe support"
+	depends on DM_PCI
+	help
+	  Say Y here if you want to enable PCIe controller support on
+	  Phytium SoCs.
+
 config PCIE_DW_MVEBU
 	bool "Enable Armada-8K PCIe driver (DesignWare core)"
 	depends on DM_PCI

drivers/pci/Makefile

@@ -38,6 +38,7 @@ obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape_fixup.o
 obj-$(CONFIG_PCIE_LAYERSCAPE_GEN4) += pcie_layerscape_gen4.o \
 				pcie_layerscape_gen4_fixup.o
 obj-$(CONFIG_PCI_XILINX) += pcie_xilinx.o
+obj-$(CONFIG_PCI_PHYTIUM) += pcie_phytium.o
 obj-$(CONFIG_PCIE_INTEL_FPGA) += pcie_intel_fpga.o
 obj-$(CONFIG_PCI_KEYSTONE) += pcie_dw_ti.o
 obj-$(CONFIG_PCIE_MEDIATEK) += pcie_mediatek.o