Merge tag 'mips-pull-2019-10-25' of git://git.denx.de/u-boot-mips

- bmips: add BCRM NAND support for BCM6368, BCM6328, BCM6362 and BCM63268 SoCs - bmips: various small fixes - mtmips: add new drivers for clock, reset-controller and pinctrl - mtmips: add support for high speed UART - mtmips: update/enhance drivers for SPI and ethernet - mtmips: add support for MMC
grygoriyS · Oct 26, 2019 · ffc379b · ffc379b
2 parents 15147dc + ec54c8c
commit ffc379b
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Showing 75 changed files with 2,327 additions and 545 deletions.
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
@@ -76,12 +76,18 @@ config ARCH_BMIPS
 
 config ARCH_MTMIPS
 	bool "Support MediaTek MIPS platforms"
+	select CLK
 	imply CMD_DM
 	select DISPLAY_CPUINFO
 	select DM
 	imply DM_ETH
 	imply DM_GPIO
+	select DM_RESET
 	select DM_SERIAL
+	select PINCTRL
+	select PINMUX
+	select PINCONF
+	select RESET_MTMIPS
 	imply DM_SPI
 	imply DM_SPI_FLASH
 	select LAST_STAGE_INIT
@@ -408,9 +414,17 @@ config SYS_ICACHE_LINE_SIZE
 	help
 	  The size of L1 Icache lines, if known at compile time.
 
+config SYS_SCACHE_LINE_SIZE
+	int
+	default 0
+	help
+	  The size of L2 cache lines, if known at compile time.
+
+
 config SYS_CACHE_SIZE_AUTO
 	def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \
-		SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0
+		SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0 && \
+		SYS_SCACHE_LINE_SIZE = 0
 	help
 	  Select this (or let it be auto-selected by not defining any cache
 	  sizes) in order to allow U-Boot to automatically detect the sizes

diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
@@ -10,6 +10,7 @@ dtb-$(CONFIG_TARGET_BOSTON) += img,boston.dtb
 dtb-$(CONFIG_TARGET_MALTA) += mti,malta.dtb
 dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb
 dtb-$(CONFIG_TARGET_XILFPGA) += nexys4ddr.dtb
+dtb-$(CONFIG_BOARD_BROADCOM_BCM968380GERG) += brcm,bcm968380gerg.dtb
 dtb-$(CONFIG_BOARD_COMTREND_AR5315U) += comtrend,ar-5315u.dtb
 dtb-$(CONFIG_BOARD_COMTREND_AR5387UN) += comtrend,ar-5387un.dtb
 dtb-$(CONFIG_BOARD_COMTREND_CT5361) += comtrend,ct-5361.dtb
@@ -19,10 +20,9 @@ dtb-$(CONFIG_BOARD_HUAWEI_HG556A) += huawei,hg556a.dtb
 dtb-$(CONFIG_BOARD_NETGEAR_CG3100D) += netgear,cg3100d.dtb
 dtb-$(CONFIG_BOARD_NETGEAR_DGND3700V2) += netgear,dgnd3700v2.dtb
 dtb-$(CONFIG_BOARD_SAGEM_FAST1704) += sagem,[email protected]
+dtb-$(CONFIG_BOARD_SFR_NB4_SER) += sfr,nb4-ser.dtb
 dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb
 dtb-$(CONFIG_TARGET_JZ4780_CI20) += ci20.dtb
-dtb-$(CONFIG_SOC_BMIPS_BCM6358) += sfr,nb4-ser.dtb
-dtb-$(CONFIG_SOC_BMIPS_BCM6838) += brcm,bcm968380gerg.dtb
 dtb-$(CONFIG_SOC_LUTON) += luton_pcb090.dtb luton_pcb091.dtb
 dtb-$(CONFIG_SOC_OCELOT) += ocelot_pcb120.dtb ocelot_pcb123.dtb
 dtb-$(CONFIG_SOC_JR2) += jr2_pcb110.dtb jr2_pcb111.dtb serval2_pcb112.dtb

diff --git a/arch/mips/dts/brcm,bcm63268.dtsi b/arch/mips/dts/brcm,bcm63268.dtsi
@@ -141,6 +141,24 @@
 			status = "disabled";
 		};
 
+		nand: nand-controller@10000200 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "brcm,nand-bcm6368",
+				     "brcm,brcmnand-v4.0",
+				     "brcm,brcmnand";
+			reg-names = "nand",
+				    "nand-cache",
+				    "nand-int-base";
+			reg = <0x10000200 0x180>,
+			      <0x10000600 0x200>,
+			      <0x100000b0 0x10>;
+			clocks = <&periph_clk BCM63268_CLK_NAND>;
+			clock-names = "nand";
+
+			status = "disabled";
+		};
+
 		periph_pwr: power-controller@1000184c {
 			compatible = "brcm,bcm6328-power-domain";
 			reg = <0x1000184c 0x4>;

diff --git a/arch/mips/dts/brcm,bcm6328.dtsi b/arch/mips/dts/brcm,bcm6328.dtsi
@@ -124,6 +124,22 @@
 			status = "disabled";
 		};
 
+		nand: nand-controller@10000200 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "brcm,nand-bcm6368",
+				     "brcm,brcmnand-v2.2",
+				     "brcm,brcmnand";
+			reg-names = "nand",
+				    "nand-cache",
+				    "nand-int-base";
+			reg = <0x10000200 0x180>,
+			      <0x10000400 0x200>,
+			      <0x100000b0 0x10>;
+
+			status = "disabled";
+		};
+
 		leds: led-controller@10000800 {
 			compatible = "brcm,bcm6328-leds";
 			reg = <0x10000800 0x24>;

diff --git a/arch/mips/dts/brcm,bcm6362.dtsi b/arch/mips/dts/brcm,bcm6362.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright (C) 2018 Ãlvaro FernÃ¡ndez Rojas <[email protected]>
+ * Copyright (C) 2018 Álvaro Fernández Rojas <[email protected]>
  */
 
 #include <dt-bindings/clock/bcm6362-clock.h>
@@ -135,6 +135,24 @@
 			status = "disabled";
 		};
 
+		nand: nand-controller@10000200 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "brcm,nand-bcm6368",
+				     "brcm,brcmnand-v2.2",
+				     "brcm,brcmnand";
+			reg-names = "nand",
+				    "nand-cache",
+				    "nand-int-base";
+			reg = <0x10000200 0x180>,
+			      <0x10000600 0x200>,
+			      <0x100000b0 0x10>;
+			clocks = <&periph_clk BCM6362_CLK_NAND>;
+			clock-names = "nand";
+
+			status = "disabled";
+		};
+
 		lsspi: spi@10000800 {
 			compatible = "brcm,bcm6358-spi";
 			reg = <0x10000800 0x70c>;

diff --git a/arch/mips/dts/brcm,bcm6368.dtsi b/arch/mips/dts/brcm,bcm6368.dtsi
@@ -146,6 +146,24 @@
 			status = "disabled";
 		};
 
+		nand: nand-controller@10000200 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "brcm,nand-bcm6368",
+				     "brcm,brcmnand-v2.1",
+				     "brcm,brcmnand";
+			reg-names = "nand",
+				    "nand-cache",
+				    "nand-int-base";
+			reg = <0x10000200 0x180>,
+			      <0x10000600 0x200>,
+			      <0x100000b0 0x10>;
+			clocks = <&periph_clk BCM6368_CLK_NAND>;
+			clock-names = "nand";
+
+			status = "disabled";
+		};
+
 		spi: spi@10000800 {
 			compatible = "brcm,bcm6358-spi";
 			reg = <0x10000800 0x70c>;

diff --git a/arch/mips/dts/comtrend,vr-3032u.dts b/arch/mips/dts/comtrend,vr-3032u.dts
@@ -99,6 +99,19 @@
 	};
 };
 
+&nand {
+	status = "okay";
+
+	nandcs@0 {
+		compatible = "brcm,nandcs";
+		reg = <0>;
+		nand-ecc-strength = <15>;
+		nand-ecc-step-size = <512>;
+		nand-on-flash-bbt;
+		brcm,nand-oob-sector-size = <64>;
+	};
+};
+
 &ohci {
 	status = "okay";
 };

diff --git a/arch/mips/dts/gardena-smart-gateway-mt7688.dts b/arch/mips/dts/gardena-smart-gateway-mt7688.dts
@@ -85,15 +85,26 @@
 	};
 };
 
+&pinctrl {
+	state_default: pin_state {
+		p0led {
+			groups = "p0led_a";
+			function = "led";
+		};
+	};
+};
+
 &uart0 {
 	status = "okay";
-	clock-frequency = <40000000>;
 };
 
 &spi0 {
 	status = "okay";
 	num-cs = <2>;
 
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi_dual_pins>;
+
 	spi-flash@0 {
 		#address-cells = <1>;
 		#size-cells = <1>;
@@ -110,3 +121,9 @@
 		reg = <1>;
 	};
 };
+
+&eth {
+	pinctrl-names = "default";
+	pinctrl-0 = <&ephy_iot_mode>;
+	mediatek,poll-link-phy = <0>;
+};
diff --git a/arch/mips/dts/linkit-smart-7688.dts b/arch/mips/dts/linkit-smart-7688.dts
@@ -26,9 +26,17 @@
 	};
 };
 
+&pinctrl {
+	state_default: pin_state {
+		p0led {
+			groups = "p0led_a";
+			function = "led";
+		};
+	};
+};
+
 &uart2 {
 	status = "okay";
-	clock-frequency = <40000000>;
 };
 
 &spi0 {
@@ -43,3 +51,9 @@
 		reg = <0>;
 	};
 };
+
+&eth {
+	pinctrl-names = "default";
+	pinctrl-0 = <&ephy_iot_mode>;
+	mediatek,poll-link-phy = <0>;
+};