Miscellaneous pytest improvements (opencis#125)

- Makefile: remove *.bin after test - Fix tests/test_cxl_host.py race-conditions due to duplicate ports Signed-off-by: Juhyung Park <[email protected]> Signed-off-by: Kyeyoon Park <[email protected]>
gwangin · Oct 24, 2024 · 8e94157 · 8e94157
1 parent c2bac21
commit 8e94157
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Showing 3 changed files with 11 additions and 10 deletions.
diff --git a/.gitignore b/.gitignore
@@ -1,5 +1,5 @@
 __pycache__
 *.log
-.coverage
+.coverage*
 *.bin
 *.patch
diff --git a/Makefile b/Makefile
@@ -8,8 +8,9 @@ else
 endif
 
 test:
+	poetry run python3 -O -m compileall -q opencxl tests
 	poetry run pytest --cov --cov-report=term-missing -n $(NPROC)
-	rm -f mem*.bin
+	rm -f *.bin
 
 lint:
 	poetry run pylint opencxl

diff --git a/tests/test_cxl_host.py b/tests/test_cxl_host.py
@@ -276,9 +276,9 @@ async def test_cxl_host_util_client():
 @pytest.mark.asyncio
 async def test_cxl_host_type3_ete():
     # pylint: disable=protected-access
-    host_port = BASE_TEST_PORT + pytest.PORT.TEST_5 + 49
+    host_port = BASE_TEST_PORT + pytest.PORT.TEST_5
     util_port = BASE_TEST_PORT + pytest.PORT.TEST_5 + 50
-    switch_port = BASE_TEST_PORT + pytest.PORT.TEST_5 + 51
+    switch_port = BASE_TEST_PORT + pytest.PORT.TEST_5 + 60
 
     port_configs = [
         PortConfig(PORT_TYPE.USP),
@@ -357,9 +357,9 @@ async def test_cxl_host_type3_ete():
 # @pytest.mark.asyncio
 # async def test_cxl_host_type3_ete_bi_only():
 #     # pylint: disable=protected-access
-#     host_port = BASE_TEST_PORT + pytest.PORT.TEST_5 + 55
-#     util_port = BASE_TEST_PORT + pytest.PORT.TEST_5 + 56
-#     switch_port = BASE_TEST_PORT + pytest.PORT.TEST_5 + 57
+#     host_port = BASE_TEST_PORT + pytest.PORT.TEST_6
+#     util_port = BASE_TEST_PORT + pytest.PORT.TEST_6 + 50
+#     switch_port = BASE_TEST_PORT + pytest.PORT.TEST_6 + 60
 
 #     port_configs = [
 #         PortConfig(PORT_TYPE.USP),
@@ -459,9 +459,9 @@ async def test_cxl_host_type3_ete():
 # @pytest.mark.asyncio
 # async def test_cxl_host_type2_ete():
 #     # pylint: disable=protected-access
-#     host_port = BASE_TEST_PORT + pytest.PORT.TEST_5 + 52
-#     util_port = BASE_TEST_PORT + pytest.PORT.TEST_5 + 53
-#     switch_port = BASE_TEST_PORT + pytest.PORT.TEST_5 + 54
+#     host_port = BASE_TEST_PORT + pytest.PORT.TEST_7
+#     util_port = BASE_TEST_PORT + pytest.PORT.TEST_7 + 50
+#     switch_port = BASE_TEST_PORT + pytest.PORT.TEST_7 + 60
 
 #     port_configs = [
 #         PortConfig(PORT_TYPE.USP),