GlobalISel: legalize conditional branches on AArch64.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279565 91177308-0d34-0410-b5e6-96231b3b80d8
hacxman · Aug 23, 2016 · 2956257 · 2956257
1 parent 1bb228f
commit 2956257
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Showing 5 changed files with 30 additions and 1 deletion.
diff --git a/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h b/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
@@ -169,7 +169,8 @@ class MachineIRBuilder {
   ///
   /// G_BRCOND is a conditional branch to \p Dest. At the beginning of
   /// legalization, \p Ty will be a single bit (s1). Targets with interesting
-  /// flags registers may change this.
+  /// flags registers may change this. For a wider type, whether the branch is
+  /// taken must only depend on bit 0 (for now).
   ///
   /// \pre setBasicBlock or setMI must have been called.
   ///

diff --git a/lib/CodeGen/GlobalISel/MachineLegalizeHelper.cpp b/lib/CodeGen/GlobalISel/MachineLegalizeHelper.cpp
@@ -173,6 +173,13 @@ MachineLegalizeHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx,
     MI.eraseFromParent();
     return Legalized;
   }
+  case TargetOpcode::G_BRCOND: {
+    unsigned TstExt = MRI.createGenericVirtualRegister(WideSize);
+    MIRBuilder.buildAnyExtend(WideTy, TstExt, MI.getOperand(0).getReg());
+    MIRBuilder.buildBrCond(WideTy, TstExt, *MI.getOperand(1).getMBB());
+    MI.eraseFromParent();
+    return Legalized;
+  }
   }
 }
 

diff --git a/lib/CodeGen/GlobalISel/MachineLegalizer.cpp b/lib/CodeGen/GlobalISel/MachineLegalizer.cpp
@@ -30,7 +30,12 @@ MachineLegalizer::MachineLegalizer() : TablesInitialized(false) {
   DefaultActions[TargetOpcode::G_ANYEXTEND] = Legal;
   DefaultActions[TargetOpcode::G_TRUNC] = Legal;
 
+  DefaultActions[TargetOpcode::G_INTRINSIC] = Legal;
+  DefaultActions[TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS] = Legal;
+
   DefaultActions[TargetOpcode::G_ADD] = NarrowScalar;
+
+  DefaultActions[TargetOpcode::G_BRCOND] = WidenScalar;
 }
 
 void MachineLegalizer::computeTables() {

diff --git a/lib/Target/AArch64/AArch64MachineLegalizer.cpp b/lib/Target/AArch64/AArch64MachineLegalizer.cpp
@@ -62,6 +62,7 @@ AArch64MachineLegalizer::AArch64MachineLegalizer() {
     setAction({MemOp, 1, p0}, Legal);
   }
 
+  // Constants
   for (auto Ty : {s32, s64}) {
     setAction({TargetOpcode::G_CONSTANT, Ty}, Legal);
     setAction({TargetOpcode::G_FCONSTANT, Ty}, Legal);
@@ -72,8 +73,13 @@ AArch64MachineLegalizer::AArch64MachineLegalizer() {
 
   setAction({TargetOpcode::G_FCONSTANT, s16}, WidenScalar);
 
+  // Control-flow
   setAction({G_BR, LLT::unsized()}, Legal);
+  setAction({G_BRCOND, s32}, Legal);
+  for (auto Ty : {s1, s8, s16})
+    setAction({G_BRCOND, Ty}, WidenScalar);
 
+  // Pointer-handling
   setAction({G_FRAME_INDEX, p0}, Legal);
 
   setAction({G_PTRTOINT, 0, s64}, Legal);

diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir b/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir
@@ -6,6 +6,8 @@
   define void @test_simple() {
   entry:
     ret void
+  next:
+    ret void
   }
 ...
 
@@ -16,6 +18,7 @@ registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
+  - { id: 3, class: _ }
 body: |
   bb.0.entry:
     liveins: %x0, %x1, %x2, %x3
@@ -26,4 +29,11 @@ body: |
     ; CHECK: %2(64) = G_INTTOPTR { p0, s64 } %1
     %1(64) = G_PTRTOINT { s64, p0 } %0
     %2(64) = G_INTTOPTR { p0, s64 } %1
+
+    ; CHECK: [[TST32:%[0-9]+]](32) = G_ANYEXTEND s32 %3
+    ; CHECK: G_BRCOND s32 [[TST32]], %bb.1.next
+    %3(1) = G_TRUNC { s1, s64 } %0
+    G_BRCOND s1 %3, %bb.1.next
+
+  bb.1.next:
 ...