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[X86][AVX512] Add missing entries to EVEX2VEX tables
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evex2vex pass defines 2 tables which maps EVEX instructions to their VEX identical when possible. Adding all missing entries.

Differential Revision: https://reviews.llvm.org/D30501



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297126 91177308-0d34-0410-b5e6-96231b3b80d8
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@aymanmusa
aymanmusa committed Mar 7, 2017
1 parent 107e5ed commit 82804ad
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Showing 13 changed files with 317 additions and 185 deletions.
89 changes: 61 additions & 28 deletions lib/Target/X86/X86InstrTablesInfo.h
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Original file line number Diff line number Diff line change
Expand Up @@ -47,9 +47,7 @@ static const X86EvexToVexCompressTableEntry X86EvexToVex128CompressTable[] = {
{ X86::VCOMISDZrr , X86::VCOMISDrr },
{ X86::VCOMISSZrm , X86::VCOMISSrm },
{ X86::VCOMISSZrr , X86::VCOMISSrr },
{ X86::VCVTSD2SI64Zrm , X86::VCVTSD2SI64rm },
{ X86::VCVTSD2SI64Zrr , X86::VCVTSD2SI64rr },
{ X86::VCVTSD2SIZrm , X86::VCVTSD2SIrm },
{ X86::VCVTSD2SIZrr , X86::VCVTSD2SIrr },
{ X86::VCVTSD2SSZrm , X86::VCVTSD2SSrm },
{ X86::VCVTSD2SSZrr , X86::VCVTSD2SSrr },
Expand All @@ -61,11 +59,17 @@ static const X86EvexToVexCompressTableEntry X86EvexToVex128CompressTable[] = {
{ X86::VCVTSI2SSZrm_Int , X86::Int_VCVTSI2SSrm },
{ X86::VCVTSI2SSZrr , X86::VCVTSI2SSrr },
{ X86::VCVTSI2SSZrr_Int , X86::Int_VCVTSI2SSrr },
{ X86::VCVTSI642SDZrm , X86::VCVTSI2SD64rm },
{ X86::VCVTSI642SDZrm_Int , X86::Int_VCVTSI2SD64rm },
{ X86::VCVTSI642SDZrr , X86::VCVTSI2SD64rr },
{ X86::VCVTSI642SDZrr_Int , X86::Int_VCVTSI2SD64rr },
{ X86::VCVTSI642SSZrm , X86::VCVTSI2SS64rm },
{ X86::VCVTSI642SSZrm_Int , X86::Int_VCVTSI2SS64rm },
{ X86::VCVTSI642SSZrr , X86::VCVTSI2SS64rr },
{ X86::VCVTSI642SSZrr_Int , X86::Int_VCVTSI2SS64rr },
{ X86::VCVTSS2SDZrm , X86::VCVTSS2SDrm },
{ X86::VCVTSS2SDZrr , X86::VCVTSS2SDrr },
{ X86::VCVTSS2SI64Zrm , X86::VCVTSS2SI64rm },
{ X86::VCVTSS2SI64Zrr , X86::VCVTSS2SI64rr },
{ X86::VCVTSS2SIZrm , X86::VCVTSS2SIrm },
{ X86::VCVTSS2SIZrr , X86::VCVTSS2SIrr },
{ X86::VCVTTSD2SI64Zrm , X86::VCVTTSD2SI64rm },
{ X86::VCVTTSD2SI64Zrm_Int , X86::Int_VCVTTSD2SI64rm },
Expand All @@ -91,6 +95,8 @@ static const X86EvexToVexCompressTableEntry X86EvexToVex128CompressTable[] = {
{ X86::VDIVSSZrm_Int , X86::VDIVSSrm_Int },
{ X86::VDIVSSZrr , X86::VDIVSSrr },
{ X86::VDIVSSZrr_Int , X86::VDIVSSrr_Int },
{ X86::VEXTRACTPSZmr , X86::VEXTRACTPSmr },
{ X86::VEXTRACTPSZrr , X86::VEXTRACTPSrr },
{ X86::VFMADD132SDZm , X86::VFMADD132SDm },
{ X86::VFMADD132SDZm_Int , X86::VFMADD132SDm_Int },
{ X86::VFMADD132SDZr , X86::VFMADD132SDr },
Expand Down Expand Up @@ -187,36 +193,43 @@ static const X86EvexToVexCompressTableEntry X86EvexToVex128CompressTable[] = {
{ X86::VFNMSUB231SSZm_Int , X86::VFNMSUB231SSm_Int },
{ X86::VFNMSUB231SSZr , X86::VFNMSUB231SSr },
{ X86::VFNMSUB231SSZr_Int , X86::VFNMSUB231SSr_Int },
{ X86::VINSERTPSZrm , X86::VINSERTPSrm },
{ X86::VINSERTPSZrr , X86::VINSERTPSrr },
{ X86::VMAXCSDZrm , X86::VMAXCSDrm },
{ X86::VMAXCSDZrr , X86::VMAXCSDrr },
{ X86::VMAXCSSZrm , X86::VMAXCSSrm },
{ X86::VMAXCSSZrr , X86::VMAXCSSrr },
{ X86::VMAXSDZrm , X86::VMAXSDrm },
{ X86::VMAXSDZrm , X86::VMAXCSDrm },
{ X86::VMAXSDZrm_Int , X86::VMAXSDrm_Int },
{ X86::VMAXSDZrr , X86::VMAXSDrr },
{ X86::VMAXSDZrr , X86::VMAXCSDrr },
{ X86::VMAXSDZrr_Int , X86::VMAXSDrr_Int },
{ X86::VMAXSSZrm , X86::VMAXSSrm },
{ X86::VMAXSSZrm , X86::VMAXCSSrm },
{ X86::VMAXSSZrm_Int , X86::VMAXSSrm_Int },
{ X86::VMAXSSZrr , X86::VMAXSSrr },
{ X86::VMAXSSZrr , X86::VMAXCSSrr },
{ X86::VMAXSSZrr_Int , X86::VMAXSSrr_Int },
{ X86::VMINCSDZrm , X86::VMINCSDrm },
{ X86::VMINCSDZrr , X86::VMINCSDrr },
{ X86::VMINCSSZrm , X86::VMINCSSrm },
{ X86::VMINCSSZrr , X86::VMINCSSrr },
{ X86::VMINSDZrm , X86::VMINSDrm },
{ X86::VMINSDZrm , X86::VMINCSDrm },
{ X86::VMINSDZrm_Int , X86::VMINSDrm_Int },
{ X86::VMINSDZrr , X86::VMINSDrr },
{ X86::VMINSDZrr , X86::VMINCSDrr },
{ X86::VMINSDZrr_Int , X86::VMINSDrr_Int },
{ X86::VMINSSZrm , X86::VMINSSrm },
{ X86::VMINSSZrm , X86::VMINCSSrm },
{ X86::VMINSSZrm_Int , X86::VMINSSrm_Int },
{ X86::VMINSSZrr , X86::VMINSSrr },
{ X86::VMINSSZrr , X86::VMINCSSrr },
{ X86::VMINSSZrr_Int , X86::VMINSSrr_Int },
{ X86::VMOV64toSDZrr , X86::VMOV64toSDrr },
{ X86::VMOVDI2SSZrm , X86::VMOVDI2SSrm },
{ X86::VMOVDI2SSZrr , X86::VMOVDI2SSrr },
{ X86::VMOVSDto64Zmr , X86::VMOVSDto64mr },
{ X86::VMOVSDto64Zrr , X86::VMOVSDto64rr },
{ X86::VMOVSDZmr , X86::VMOVSDmr },
{ X86::VMOVSDZrm , X86::VMOVSDrm },
{ X86::VMOVSDZrr , X86::VMOVSDrr },
{ X86::VMOVSDZrr_REV , X86::VMOVSDrr_REV },
{ X86::VMOVSS2DIZmr , X86::VMOVSS2DImr },
{ X86::VMOVSS2DIZrr , X86::VMOVSS2DIrr },
{ X86::VMOVSSZmr , X86::VMOVSSmr },
{ X86::VMOVSSZrm , X86::VMOVSSrm },
{ X86::VMOVSSZrr , X86::VMOVSSrr },
Expand Down Expand Up @@ -250,6 +263,7 @@ static const X86EvexToVexCompressTableEntry X86EvexToVex128CompressTable[] = {
{ X86::VUCOMISSZrm , X86::VUCOMISSrm },
{ X86::VUCOMISSZrr , X86::VUCOMISSrr },

{ X86::VMOV64toPQIZrm , X86::VMOV64toPQIrm },
{ X86::VMOV64toPQIZrr , X86::VMOV64toPQIrr },
{ X86::VMOV64toSDZrr , X86::VMOV64toSDrr },
{ X86::VMOVDI2PDIZrm , X86::VMOVDI2PDIrm },
Expand All @@ -259,6 +273,8 @@ static const X86EvexToVexCompressTableEntry X86EvexToVex128CompressTable[] = {
{ X86::VMOVPDI2DIZmr , X86::VMOVPDI2DImr },
{ X86::VMOVPDI2DIZrr , X86::VMOVPDI2DIrr },
{ X86::VMOVPQI2QIZmr , X86::VMOVPQI2QImr },
{ X86::VMOVPQI2QIZrr , X86::VMOVPQI2QIrr },
{ X86::VMOVPQIto64Zmr , X86::VMOVPQIto64mr },
{ X86::VMOVPQIto64Zrr , X86::VMOVPQIto64rr },
{ X86::VMOVQI2PQIZrm , X86::VMOVQI2PQIrm },
{ X86::VMOVZPQILo2PQIZrr , X86::VMOVZPQILo2PQIrr },
Expand All @@ -271,6 +287,7 @@ static const X86EvexToVexCompressTableEntry X86EvexToVex128CompressTable[] = {
{ X86::VPEXTRQZrr , X86::VPEXTRQrr },
{ X86::VPEXTRWZmr , X86::VPEXTRWmr },
{ X86::VPEXTRWZrr , X86::VPEXTRWri },
{ X86::VPEXTRWZrr_REV , X86::VPEXTRWrr_REV },

{ X86::VPINSRBZrm , X86::VPINSRBrm },
{ X86::VPINSRBZrr , X86::VPINSRBrr },
Expand All @@ -294,6 +311,8 @@ static const X86EvexToVexCompressTableEntry X86EvexToVex128CompressTable[] = {
{ X86::VANDPDZ128rr , X86::VANDPDrr },
{ X86::VANDPSZ128rm , X86::VANDPSrm },
{ X86::VANDPSZ128rr , X86::VANDPSrr },
{ X86::VBROADCASTI32X2Z128m , X86::VPBROADCASTQrm },
{ X86::VBROADCASTI32X2Z128r , X86::VPBROADCASTQrr },
{ X86::VBROADCASTSSZ128m , X86::VBROADCASTSSrm },
{ X86::VBROADCASTSSZ128r , X86::VBROADCASTSSrr },
{ X86::VCVTDQ2PDZ128rm , X86::VCVTDQ2PDrm },
Expand Down Expand Up @@ -396,18 +415,18 @@ static const X86EvexToVexCompressTableEntry X86EvexToVex128CompressTable[] = {
{ X86::VMAXCPDZ128rr , X86::VMAXCPDrr },
{ X86::VMAXCPSZ128rm , X86::VMAXCPSrm },
{ X86::VMAXCPSZ128rr , X86::VMAXCPSrr },
{ X86::VMAXPDZ128rm , X86::VMAXPDrm },
{ X86::VMAXPDZ128rr , X86::VMAXPDrr },
{ X86::VMAXPSZ128rm , X86::VMAXPSrm },
{ X86::VMAXPSZ128rr , X86::VMAXPSrr },
{ X86::VMAXPDZ128rm , X86::VMAXCPDrm },
{ X86::VMAXPDZ128rr , X86::VMAXCPDrr },
{ X86::VMAXPSZ128rm , X86::VMAXCPSrm },
{ X86::VMAXPSZ128rr , X86::VMAXCPSrr },
{ X86::VMINCPDZ128rm , X86::VMINCPDrm },
{ X86::VMINCPDZ128rr , X86::VMINCPDrr },
{ X86::VMINCPSZ128rm , X86::VMINCPSrm },
{ X86::VMINCPSZ128rr , X86::VMINCPSrr },
{ X86::VMINPDZ128rm , X86::VMINPDrm },
{ X86::VMINPDZ128rr , X86::VMINPDrr },
{ X86::VMINPSZ128rm , X86::VMINPSrm },
{ X86::VMINPSZ128rr , X86::VMINPSrr },
{ X86::VMINPDZ128rm , X86::VMINCPDrm },
{ X86::VMINPDZ128rr , X86::VMINCPDrr },
{ X86::VMINPSZ128rm , X86::VMINCPSrm },
{ X86::VMINPSZ128rr , X86::VMINCPSrr },
{ X86::VMOVAPDZ128mr , X86::VMOVAPDmr },
{ X86::VMOVAPDZ128rm , X86::VMOVAPDrm },
{ X86::VMOVAPDZ128rr , X86::VMOVAPDrr },
Expand Down Expand Up @@ -510,6 +529,10 @@ static const X86EvexToVexCompressTableEntry X86EvexToVex128CompressTable[] = {
{ X86::VPANDDZ128rr , X86::VPANDrr },
{ X86::VPANDQZ128rm , X86::VPANDrm },
{ X86::VPANDQZ128rr , X86::VPANDrr },
{ X86::VPANDNDZ128rm , X86::VPANDNrm },
{ X86::VPANDNDZ128rr , X86::VPANDNrr },
{ X86::VPANDNQZ128rm , X86::VPANDNrm },
{ X86::VPANDNQZ128rr , X86::VPANDNrr },
{ X86::VPAVGBZ128rm , X86::VPAVGBrm },
{ X86::VPAVGBZ128rr , X86::VPAVGBrr },
{ X86::VPAVGWZ128rm , X86::VPAVGWrm },
Expand Down Expand Up @@ -724,6 +747,12 @@ static const X86EvexToVexCompressTableEntry X86EvexToVex128CompressTable[] = {
{ X86::VANDPDZ256rr , X86::VANDPDYrr },
{ X86::VANDPSZ256rm , X86::VANDPSYrm },
{ X86::VANDPSZ256rr , X86::VANDPSYrr },
{ X86::VBROADCASTF32X2Z256m , X86::VBROADCASTSDYrm },
{ X86::VBROADCASTF32X2Z256r , X86::VBROADCASTSDYrr },
{ X86::VBROADCASTF32X4Z256rm , X86::VBROADCASTF128 },
{ X86::VBROADCASTI32X2Z256m , X86::VPBROADCASTQYrm },
{ X86::VBROADCASTI32X2Z256r , X86::VPBROADCASTQYrr },
{ X86::VBROADCASTI32X4Z256rm , X86::VBROADCASTI128 },
{ X86::VBROADCASTSDZ256m , X86::VBROADCASTSDYrm },
{ X86::VBROADCASTSDZ256r , X86::VBROADCASTSDYrr },
{ X86::VBROADCASTSSZ256m , X86::VBROADCASTSSYrm },
Expand Down Expand Up @@ -844,18 +873,18 @@ static const X86EvexToVexCompressTableEntry X86EvexToVex128CompressTable[] = {
{ X86::VMAXCPDZ256rr , X86::VMAXCPDYrr },
{ X86::VMAXCPSZ256rm , X86::VMAXCPSYrm },
{ X86::VMAXCPSZ256rr , X86::VMAXCPSYrr },
{ X86::VMAXPDZ256rm , X86::VMAXPDYrm },
{ X86::VMAXPDZ256rr , X86::VMAXPDYrr },
{ X86::VMAXPSZ256rm , X86::VMAXPSYrm },
{ X86::VMAXPSZ256rr , X86::VMAXPSYrr },
{ X86::VMAXPDZ256rm , X86::VMAXCPDYrm },
{ X86::VMAXPDZ256rr , X86::VMAXCPDYrr },
{ X86::VMAXPSZ256rm , X86::VMAXCPSYrm },
{ X86::VMAXPSZ256rr , X86::VMAXCPSYrr },
{ X86::VMINCPDZ256rm , X86::VMINCPDYrm },
{ X86::VMINCPDZ256rr , X86::VMINCPDYrr },
{ X86::VMINCPSZ256rm , X86::VMINCPSYrm },
{ X86::VMINCPSZ256rr , X86::VMINCPSYrr },
{ X86::VMINPDZ256rm , X86::VMINPDYrm },
{ X86::VMINPDZ256rr , X86::VMINPDYrr },
{ X86::VMINPSZ256rm , X86::VMINPSYrm },
{ X86::VMINPSZ256rr , X86::VMINPSYrr },
{ X86::VMINPDZ256rm , X86::VMINCPDYrm },
{ X86::VMINPDZ256rr , X86::VMINCPDYrr },
{ X86::VMINPSZ256rm , X86::VMINCPSYrm },
{ X86::VMINPSZ256rr , X86::VMINCPSYrr },
{ X86::VMOVAPDZ256mr , X86::VMOVAPDYmr },
{ X86::VMOVAPDZ256rm , X86::VMOVAPDYrm },
{ X86::VMOVAPDZ256rr , X86::VMOVAPDYrr },
Expand Down Expand Up @@ -950,6 +979,10 @@ static const X86EvexToVexCompressTableEntry X86EvexToVex128CompressTable[] = {
{ X86::VPANDDZ256rr , X86::VPANDYrr },
{ X86::VPANDQZ256rm , X86::VPANDYrm },
{ X86::VPANDQZ256rr , X86::VPANDYrr },
{ X86::VPANDNDZ256rm , X86::VPANDNYrm },
{ X86::VPANDNDZ256rr , X86::VPANDNYrr },
{ X86::VPANDNQZ256rm , X86::VPANDNYrm },
{ X86::VPANDNQZ256rr , X86::VPANDNYrr },
{ X86::VPAVGBZ256rm , X86::VPAVGBYrm },
{ X86::VPAVGBZ256rr , X86::VPAVGBYrr },
{ X86::VPAVGWZ256rm , X86::VPAVGWYrm },
Expand Down
2 changes: 1 addition & 1 deletion test/CodeGen/X86/avx512-mov.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -4,7 +4,7 @@
define i32 @test1(float %x) {
; CHECK-LABEL: test1:
; CHECK: ## BB#0:
; CHECK-NEXT: vmovd %xmm0, %eax ## encoding: [0x62,0xf1,0x7d,0x08,0x7e,0xc0]
; CHECK-NEXT: vmovd %xmm0, %eax ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x7e,0xc0]
; CHECK-NEXT: retq ## encoding: [0xc3]
%res = bitcast float %x to i32
ret i32 %res
Expand Down
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