[globalisel][tablegen] Fix small spelling nits. NFC

ComplexRendererFn -> ComplexRendererFns
Corrected a couple lingering references to tied operands that were missed.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316237 91177308-0d34-0410-b5e6-96231b3b80d8

include/llvm/CodeGen/GlobalISel/InstructionSelector.h

@@ -276,13 +276,13 @@ class InstructionSelector {
   virtual bool select(MachineInstr &I) const = 0;
 
 protected:
-  using ComplexRendererFn =
+  using ComplexRendererFns =
       Optional<SmallVector<std::function<void(MachineInstrBuilder &)>, 4>>;
   using RecordedMIVector = SmallVector<MachineInstr *, 4>;
   using NewMIVector = SmallVector<MachineInstrBuilder, 4>;
 
   struct MatcherState {
-    std::vector<ComplexRendererFn::value_type> Renderers;
+    std::vector<ComplexRendererFns::value_type> Renderers;
     RecordedMIVector MIs;
 
     MatcherState(unsigned MaxRenderers);

include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h

@@ -297,7 +297,7 @@ bool InstructionSelector::executeMatchTable(
                    << "), ComplexPredicateID=" << ComplexPredicateID << ")\n");
       assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
       // FIXME: Use std::invoke() when it's available.
-      ComplexRendererFn Renderer =
+      ComplexRendererFns Renderer =
           (ISel.*MatcherInfo.ComplexPredicates[ComplexPredicateID])(
               State.MIs[InsnID]->getOperand(OpIdx));
       if (Renderer.hasValue())

lib/Target/AArch64/AArch64InstructionSelector.cpp

@@ -64,31 +64,31 @@ class AArch64InstructionSelector : public InstructionSelector {
   bool selectCompareBranch(MachineInstr &I, MachineFunction &MF,
                            MachineRegisterInfo &MRI) const;
 
-  ComplexRendererFn selectArithImmed(MachineOperand &Root) const;
+  ComplexRendererFns selectArithImmed(MachineOperand &Root) const;
 
-  ComplexRendererFn selectAddrModeUnscaled(MachineOperand &Root,
-                                           unsigned Size) const;
+  ComplexRendererFns selectAddrModeUnscaled(MachineOperand &Root,
+                                            unsigned Size) const;
 
-  ComplexRendererFn selectAddrModeUnscaled8(MachineOperand &Root) const {
+  ComplexRendererFns selectAddrModeUnscaled8(MachineOperand &Root) const {
     return selectAddrModeUnscaled(Root, 1);
   }
-  ComplexRendererFn selectAddrModeUnscaled16(MachineOperand &Root) const {
+  ComplexRendererFns selectAddrModeUnscaled16(MachineOperand &Root) const {
     return selectAddrModeUnscaled(Root, 2);
   }
-  ComplexRendererFn selectAddrModeUnscaled32(MachineOperand &Root) const {
+  ComplexRendererFns selectAddrModeUnscaled32(MachineOperand &Root) const {
     return selectAddrModeUnscaled(Root, 4);
   }
-  ComplexRendererFn selectAddrModeUnscaled64(MachineOperand &Root) const {
+  ComplexRendererFns selectAddrModeUnscaled64(MachineOperand &Root) const {
     return selectAddrModeUnscaled(Root, 8);
   }
-  ComplexRendererFn selectAddrModeUnscaled128(MachineOperand &Root) const {
+  ComplexRendererFns selectAddrModeUnscaled128(MachineOperand &Root) const {
     return selectAddrModeUnscaled(Root, 16);
   }
 
-  ComplexRendererFn selectAddrModeIndexed(MachineOperand &Root,
-                                          unsigned Size) const;
+  ComplexRendererFns selectAddrModeIndexed(MachineOperand &Root,
+                                           unsigned Size) const;
   template <int Width>
-  ComplexRendererFn selectAddrModeIndexed(MachineOperand &Root) const {
+  ComplexRendererFns selectAddrModeIndexed(MachineOperand &Root) const {
     return selectAddrModeIndexed(Root, Width / 8);
   }
 
@@ -1373,7 +1373,7 @@ bool AArch64InstructionSelector::select(MachineInstr &I) const {
 /// SelectArithImmed - Select an immediate value that can be represented as
 /// a 12-bit value shifted left by either 0 or 12.  If so, return true with
 /// Val set to the 12-bit value and Shift set to the shifter operand.
-InstructionSelector::ComplexRendererFn
+InstructionSelector::ComplexRendererFns
 AArch64InstructionSelector::selectArithImmed(MachineOperand &Root) const {
   MachineInstr &MI = *Root.getParent();
   MachineBasicBlock &MBB = *MI.getParent();
@@ -1423,7 +1423,7 @@ AArch64InstructionSelector::selectArithImmed(MachineOperand &Root) const {
 /// immediate addressing mode.  The "Size" argument is the size in bytes of the
 /// memory reference, which is needed here to know what is valid for a scaled
 /// immediate.
-InstructionSelector::ComplexRendererFn
+InstructionSelector::ComplexRendererFns
 AArch64InstructionSelector::selectAddrModeUnscaled(MachineOperand &Root,
                                                    unsigned Size) const {
   MachineRegisterInfo &MRI =
@@ -1467,7 +1467,7 @@ AArch64InstructionSelector::selectAddrModeUnscaled(MachineOperand &Root,
 /// Select a "register plus scaled unsigned 12-bit immediate" address.  The
 /// "Size" argument is the size in bytes of the memory reference, which
 /// determines the scale.
-InstructionSelector::ComplexRendererFn
+InstructionSelector::ComplexRendererFns
 AArch64InstructionSelector::selectAddrModeIndexed(MachineOperand &Root,
                                                   unsigned Size) const {
   MachineRegisterInfo &MRI =

test/TableGen/GlobalISelEmitter.td

@@ -53,7 +53,7 @@ def HasC : Predicate<"Subtarget->hasC()"> { let RecomputePerFunction = 1; }
 
 // CHECK-LABEL: #ifdef GET_GLOBALISEL_TEMPORARIES_DECL
 // CHECK-NEXT:    mutable MatcherState State;
-// CHECK-NEXT:    typedef ComplexRendererFn(MyTargetInstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const;
+// CHECK-NEXT:    typedef ComplexRendererFns(MyTargetInstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const;
 // CHECK-NEXT:    const MatcherInfoTy<PredicateBitset, ComplexMatcherMemFn> MatcherInfo;
 // CHECK-NEXT:    static MyTargetInstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[];
 // CHECK-NEXT:  #endif // ifdef GET_GLOBALISEL_TEMPORARIES_DECL

utils/TableGen/GlobalISelEmitter.cpp

@@ -672,7 +672,7 @@ class OperandPredicateMatcher {
   /// but OPM_Int must have priority over OPM_RegBank since constant integers
   /// are represented by a virtual register defined by a G_CONSTANT instruction.
   enum PredicateKind {
-    OPM_Tie,
+    OPM_SameOperand,
     OPM_ComplexPattern,
     OPM_IntrinsicID,
     OPM_Instruction,
@@ -724,14 +724,14 @@ PredicateListMatcher<OperandPredicateMatcher>::getNoPredicateComment() const {
 /// Generates code to check that a register operand is defined by the same exact
 /// one as another.
 class SameOperandMatcher : public OperandPredicateMatcher {
-  std::string TiedTo;
+  std::string MatchingName;
 
 public:
-  SameOperandMatcher(StringRef TiedTo)
-      : OperandPredicateMatcher(OPM_Tie), TiedTo(TiedTo) {}
+  SameOperandMatcher(StringRef MatchingName)
+      : OperandPredicateMatcher(OPM_SameOperand), MatchingName(MatchingName) {}
 
   static bool classof(const OperandPredicateMatcher *P) {
-    return P->getKind() == OPM_Tie;
+    return P->getKind() == OPM_SameOperand;
   }
 
   void emitPredicateOpcodes(MatchTable &Table, RuleMatcher &Rule,
@@ -2094,7 +2094,7 @@ void SameOperandMatcher::emitPredicateOpcodes(MatchTable &Table,
                                               RuleMatcher &Rule,
                                               unsigned InsnVarID,
                                               unsigned OpIdx) const {
-  const OperandMatcher &OtherOM = Rule.getOperandMatcher(TiedTo);
+  const OperandMatcher &OtherOM = Rule.getOperandMatcher(MatchingName);
   unsigned OtherInsnVarID = Rule.getInsnVarID(OtherOM.getInstructionMatcher());
 
   Table << MatchTable::Opcode("GIM_CheckIsSameOperand")
@@ -2982,7 +2982,7 @@ void GlobalISelEmitter::run(raw_ostream &OS) {
   OS << "#ifdef GET_GLOBALISEL_TEMPORARIES_DECL\n"
      << "  mutable MatcherState State;\n"
      << "  typedef "
-        "ComplexRendererFn("
+        "ComplexRendererFns("
      << Target.getName()
      << "InstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const;\n"
      << "  const MatcherInfoTy<PredicateBitset, ComplexMatcherMemFn> "