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[SystemZ] Enable machine scheduler.
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The machine scheduler (before register allocation) is enabled by default for
SystemZ.

The SelectionDAG scheduling preference now becomes source order scheduling
(was regpressure).

Review: Ulrich Weigand
https://reviews.llvm.org/D37977

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315063 91177308-0d34-0410-b5e6-96231b3b80d8
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@JonPsson
JonPsson committed Oct 6, 2017
1 parent 94302cb commit da3da48
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Showing 46 changed files with 1,271 additions and 8,937 deletions.
5 changes: 5 additions & 0 deletions lib/Target/SystemZ/SystemZSubtarget.h
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Original file line number Diff line number Diff line change
Expand Up @@ -91,6 +91,11 @@ class SystemZSubtarget : public SystemZGenSubtargetInfo {
return &TSInfo;
}

// True if the subtarget should run MachineScheduler after aggressive
// coalescing. This currently replaces the SelectionDAG scheduler with the
// "source" order scheduler.
bool enableMachineScheduler() const override { return true; }

// This is important for reducing register pressure in vector code.
bool useAA() const override { return true; }

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10 changes: 7 additions & 3 deletions test/CodeGen/SystemZ/alloca-01.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -13,6 +13,10 @@ declare i64 @bar(i8 *%a, i8 *%b, i8 *%c, i8 *%d, i8 *%e, i64 %f, i64 %g)
; Allocate %length bytes and take addresses based on the result.
; There are two stack arguments, so an offset of 160 + 2 * 8 == 176
; is added to the copy of %r15.
;
; NOTE: 'la %r0, 177(%r1)' is actually an expected fail as it would
; be better (and possible) to load into %r3 directly.
;
define i64 @f1(i64 %length, i64 %index) {
; FIXME: a better sequence would be:
;
Expand All @@ -29,12 +33,12 @@ define i64 @f1(i64 %length, i64 %index) {
; CHECK: lgr %r15, [[REG2]]
;
; CHECK-A-LABEL: f1:
; CHECK-A: lgr %r15, %r1
; CHECK-A: la %r2, 176(%r1)
; CHECK-A-DAG: lgr %r15, %r1
; CHECK-A-DAG: la %r2, 176(%r1)
;
; CHECK-B-LABEL: f1:
; CHECK-B: lgr %r15, %r1
; CHECK-B: la %r3, 177(%r1)
; CHECK-B: la %r0, 177(%r1)
;
; CHECK-C-LABEL: f1:
; CHECK-C: lgr %r15, %r1
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14 changes: 7 additions & 7 deletions test/CodeGen/SystemZ/alloca-02.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -10,29 +10,29 @@ declare i64 @bar(i8 *%a)

define i64 @f1(i64 %length, i64 %index) {
; CHECK-A-LABEL: f1:
; CHECK-A: lgr %r15, [[ADDR:%r[1-5]]]
; CHECK-A: la %r2, 160([[ADDR]])
; CHECK-A-DAG: lgr %r15, [[ADDR:%r[1-5]]]
; CHECK-A-DAG: la %r2, 160([[ADDR]])
; CHECK-A: mvi 0(%r2), 0
;
; CHECK-B-LABEL: f1:
; CHECK-B: lgr %r15, [[ADDR:%r[1-5]]]
; CHECK-B: la %r2, 160([[ADDR]])
; CHECK-B-DAG: lgr %r15, [[ADDR:%r[1-5]]]
; CHECK-B-DAG: la %r2, 160([[ADDR]])
; CHECK-B: mvi 4095(%r2), 1
;
; CHECK-C-LABEL: f1:
; CHECK-C: lgr %r15, [[ADDR:%r[1-5]]]
; CHECK-C-DAG: lgr %r15, [[ADDR:%r[1-5]]]
; CHECK-C-DAG: la %r2, 160([[ADDR]])
; CHECK-C-DAG: lhi [[TMP:%r[0-5]]], 2
; CHECK-C: stc [[TMP]], 0({{%r3,%r2|%r2,%r3}})
;
; CHECK-D-LABEL: f1:
; CHECK-D: lgr %r15, [[ADDR:%r[1-5]]]
; CHECK-D-DAG: lgr %r15, [[ADDR:%r[1-5]]]
; CHECK-D-DAG: la %r2, 160([[ADDR]])
; CHECK-D-DAG: lhi [[TMP:%r[0-5]]], 3
; CHECK-D: stc [[TMP]], 4095({{%r3,%r2|%r2,%r3}})
;
; CHECK-E-LABEL: f1:
; CHECK-E: lgr %r15, [[ADDR:%r[1-5]]]
; CHECK-E-DAG: lgr %r15, [[ADDR:%r[1-5]]]
; CHECK-E-DAG: la %r2, 160([[ADDR]])
; CHECK-E-DAG: lhi [[TMP:%r[0-5]]], 4
; CHECK-E: stcy [[TMP]], 4096({{%r3,%r2|%r2,%r3}})
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36 changes: 18 additions & 18 deletions test/CodeGen/SystemZ/alloca-03.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -15,13 +15,13 @@ define void @f0() {
; Allocate %len * 8, no need to align stack.
define void @f1(i64 %len) {
; CHECK-LABEL: f1:
; CHECK: sllg %r0, %r2, 3
; CHECK: lgr %r1, %r15
; CHECK-DAG: sllg %r0, %r2, 3
; CHECK-DAG: lgr %r1, %r15
; CHECK: sgr %r1, %r0
; CHECK-NOT: ngr
; CHECK: lgr %r15, %r1
; CHECK: la %r1, 160(%r1)
; CHECK: mvghi 0(%r1), 10
; CHECK-DAG: lgr %r15, %r1
; CHECK-DAG: la %r2, 160(%r1)
; CHECK: mvghi 0(%r2), 10
%x = alloca i64, i64 %len
store volatile i64 10, i64* %x
ret void
Expand All @@ -31,10 +31,10 @@ define void @f1(i64 %len) {
define void @f2() {
; CHECK-LABEL: f2:
; CHECK: aghi %r1, -128
; CHECK: lgr %r15, %r1
; CHECK: la %r1, 280(%r1)
; CHECK: nill %r1, 65408
; CHECK: mvghi 0(%r1), 10
; CHECK-DAG: lgr %r15, %r1
; CHECK-DAG: la %r2, 280(%r1)
; CHECK-DAG: nill %r2, 65408
; CHECK: mvghi 0(%r2), 10
%x = alloca i64, i64 1, align 128
store volatile i64 10, i64* %x, align 128
ret void
Expand All @@ -43,14 +43,14 @@ define void @f2() {
; Dynamic alloca, align 128.
define void @f3(i64 %len) {
; CHECK-LABEL: f3:
; CHECK: sllg %r1, %r2, 3
; CHECK: la %r0, 120(%r1)
; CHECK: lgr %r1, %r15
; CHECK-DAG: sllg %r2, %r2, 3
; CHECK-DAG: la %r0, 120(%r2)
; CHECK-DAG: lgr %r1, %r15
; CHECK: sgr %r1, %r0
; CHECK: la %r2, 280(%r1)
; CHECK: nill %r2, 65408
; CHECK: lgr %r15, %r1
; CHECK: la %r1, 280(%r1)
; CHECK: nill %r1, 65408
; CHECK: mvghi 0(%r1), 10
; CHECK: mvghi 0(%r2), 10
%x = alloca i64, i64 %len, align 128
store volatile i64 10, i64* %x, align 128
ret void
Expand All @@ -73,10 +73,10 @@ define void @f5() {

; CHECK: lgr %r1, %r15
; CHECK: aghi %r1, -128
; CHECK: la %r2, 280(%r1)
; CHECK: nill %r2, 65408
; CHECK: lgr %r15, %r1
; CHECK: la %r1, 280(%r1)
; CHECK: nill %r1, 65408
; CHECK: mvhi 0(%r1), 10
; CHECK: mvhi 0(%r2), 10
%x = alloca i32, i64 1, align 128
store volatile i32 10, i32* %x
ret void
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4 changes: 2 additions & 2 deletions test/CodeGen/SystemZ/args-06.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -5,12 +5,12 @@

define i8 @f1(i8 %a, i8 %b, i8 %c, i8 %d, i8 %e, i8 %f, i8 %g) {
; CHECK-LABEL: f1:
; CHECK: lb {{%r[0-5]}}, 175(%r15)
; CHECK: lb {{%r[0-5]}}, 167(%r15)
; CHECK: ar %r2, %r3
; CHECK: ar %r2, %r4
; CHECK: ar %r2, %r5
; CHECK: ar %r2, %r6
; CHECK: lb {{%r[0-5]}}, 167(%r15)
; CHECK: lb {{%r[0-5]}}, 175(%r15)
; CHECK: br %r14
%addb = add i8 %a, %b
%addc = add i8 %addb, %c
Expand Down
8 changes: 4 additions & 4 deletions test/CodeGen/SystemZ/atomicrmw-add-01.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -15,8 +15,8 @@
define i8 @f1(i8 *%src, i8 %b) {
; CHECK-LABEL: f1:
; CHECK: risbg %r1, %r2, 0, 189, 0{{$}}
; CHECK: sll [[SHIFT:%r[0-9]+]], 3
; CHECK: l [[OLD:%r[0-9]+]], 0(%r1)
; CHECK-DAG: sll [[SHIFT:%r[0-9]+]], 3
; CHECK-DAG: l [[OLD:%r[0-9]+]], 0(%r1)
; CHECK: [[LABEL:\.[^:]*]]:
; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
; CHECK: ar [[ROT]], %r3
Expand Down Expand Up @@ -49,8 +49,8 @@ define i8 @f1(i8 *%src, i8 %b) {
define i8 @f2(i8 *%src) {
; CHECK-LABEL: f2:
; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0
; CHECK: sll %r2, 3
; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK-DAG: sll %r2, 3
; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK: [[LABEL:\.[^:]*]]:
; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
; CHECK: afi [[ROT]], -2147483648
Expand Down
8 changes: 4 additions & 4 deletions test/CodeGen/SystemZ/atomicrmw-add-02.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -15,8 +15,8 @@
define i16 @f1(i16 *%src, i16 %b) {
; CHECK-LABEL: f1:
; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
; CHECK: sll %r2, 3
; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK-DAG: sll %r2, 3
; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK: [[LABEL:\.[^:]*]]:
; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
; CHECK: ar [[ROT]], %r3
Expand Down Expand Up @@ -49,8 +49,8 @@ define i16 @f1(i16 *%src, i16 %b) {
define i16 @f2(i16 *%src) {
; CHECK-LABEL: f2:
; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0
; CHECK: sll %r2, 3
; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK-DAG: sll %r2, 3
; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK: [[LABEL:\.[^:]*]]:
; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
; CHECK: afi [[ROT]], -2147483648
Expand Down
4 changes: 2 additions & 2 deletions test/CodeGen/SystemZ/atomicrmw-and-01.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -49,8 +49,8 @@ define i8 @f1(i8 *%src, i8 %b) {
define i8 @f2(i8 *%src) {
; CHECK-LABEL: f2:
; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0
; CHECK: sll %r2, 3
; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK-DAG: sll %r2, 3
; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK: [[LABEL:\.[^:]*]]:
; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
; CHECK: nilh [[ROT]], 33023
Expand Down
8 changes: 4 additions & 4 deletions test/CodeGen/SystemZ/atomicrmw-and-02.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -15,8 +15,8 @@
define i16 @f1(i16 *%src, i16 %b) {
; CHECK-LABEL: f1:
; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
; CHECK: sll %r2, 3
; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK-DAG: sll %r2, 3
; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK: [[LABEL:\.[^:]*]]:
; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
; CHECK: nr [[ROT]], %r3
Expand Down Expand Up @@ -50,8 +50,8 @@ define i16 @f1(i16 *%src, i16 %b) {
define i16 @f2(i16 *%src) {
; CHECK-LABEL: f2:
; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
; CHECK: sll %r2, 3
; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK-DAG: sll %r2, 3
; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK: [[LABEL:\.[^:]*]]:
; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
; CHECK: nilh [[ROT]], 32768
Expand Down
16 changes: 8 additions & 8 deletions test/CodeGen/SystemZ/atomicrmw-minmax-01.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -15,8 +15,8 @@
define i8 @f1(i8 *%src, i8 %b) {
; CHECK-LABEL: f1:
; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
; CHECK: sll %r2, 3
; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK-DAG: sll %r2, 3
; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK: [[LOOP:\.[^:]*]]:
; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
; CHECK: crjle [[ROT]], %r3, [[KEEP:\..*]]
Expand Down Expand Up @@ -51,8 +51,8 @@ define i8 @f1(i8 *%src, i8 %b) {
define i8 @f2(i8 *%src, i8 %b) {
; CHECK-LABEL: f2:
; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
; CHECK: sll %r2, 3
; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK-DAG: sll %r2, 3
; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK: [[LOOP:\.[^:]*]]:
; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
; CHECK: crjhe [[ROT]], %r3, [[KEEP:\..*]]
Expand Down Expand Up @@ -87,8 +87,8 @@ define i8 @f2(i8 *%src, i8 %b) {
define i8 @f3(i8 *%src, i8 %b) {
; CHECK-LABEL: f3:
; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
; CHECK: sll %r2, 3
; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK-DAG: sll %r2, 3
; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK: [[LOOP:\.[^:]*]]:
; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
; CHECK: clrjle [[ROT]], %r3, [[KEEP:\..*]]
Expand Down Expand Up @@ -123,8 +123,8 @@ define i8 @f3(i8 *%src, i8 %b) {
define i8 @f4(i8 *%src, i8 %b) {
; CHECK-LABEL: f4:
; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
; CHECK: sll %r2, 3
; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK-DAG: sll %r2, 3
; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK: [[LOOP:\.[^:]*]]:
; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
; CHECK: clrjhe [[ROT]], %r3, [[KEEP:\..*]]
Expand Down
16 changes: 8 additions & 8 deletions test/CodeGen/SystemZ/atomicrmw-minmax-02.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -15,8 +15,8 @@
define i16 @f1(i16 *%src, i16 %b) {
; CHECK-LABEL: f1:
; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
; CHECK: sll %r2, 3
; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK-DAG: sll %r2, 3
; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK: [[LOOP:\.[^:]*]]:
; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
; CHECK: crjle [[ROT]], %r3, [[KEEP:\..*]]
Expand Down Expand Up @@ -51,8 +51,8 @@ define i16 @f1(i16 *%src, i16 %b) {
define i16 @f2(i16 *%src, i16 %b) {
; CHECK-LABEL: f2:
; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
; CHECK: sll %r2, 3
; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK-DAG: sll %r2, 3
; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK: [[LOOP:\.[^:]*]]:
; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
; CHECK: crjhe [[ROT]], %r3, [[KEEP:\..*]]
Expand Down Expand Up @@ -87,8 +87,8 @@ define i16 @f2(i16 *%src, i16 %b) {
define i16 @f3(i16 *%src, i16 %b) {
; CHECK-LABEL: f3:
; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
; CHECK: sll %r2, 3
; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK-DAG: sll %r2, 3
; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK: [[LOOP:\.[^:]*]]:
; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
; CHECK: clrjle [[ROT]], %r3, [[KEEP:\..*]]
Expand Down Expand Up @@ -123,8 +123,8 @@ define i16 @f3(i16 *%src, i16 %b) {
define i16 @f4(i16 *%src, i16 %b) {
; CHECK-LABEL: f4:
; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
; CHECK: sll %r2, 3
; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK-DAG: sll %r2, 3
; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK: [[LOOP:\.[^:]*]]:
; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
; CHECK: clrjhe [[ROT]], %r3, [[KEEP:\..*]]
Expand Down
4 changes: 2 additions & 2 deletions test/CodeGen/SystemZ/atomicrmw-minmax-04.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -133,8 +133,8 @@ define i64 @f9(i64 %dummy, i64 %base, i64 %index, i64 %b) {
; Check that constants are handled.
define i64 @f10(i64 %dummy, i64 *%ptr) {
; CHECK-LABEL: f10:
; CHECK: lghi [[LIMIT:%r[0-9]+]], 42
; CHECK: lg %r2, 0(%r3)
; CHECK-DAG: lghi [[LIMIT:%r[0-9]+]], 42
; CHECK-DAG: lg %r2, 0(%r3)
; CHECK: j [[LOOP:\.[^:]*]]
; CHECK: [[BB1:\.[^:]*]]:
; CHECK: csg %r2, [[NEW:%r[0-9]+]], 0(%r3)
Expand Down
8 changes: 4 additions & 4 deletions test/CodeGen/SystemZ/atomicrmw-nand-01.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -15,8 +15,8 @@
define i8 @f1(i8 *%src, i8 %b) {
; CHECK-LABEL: f1:
; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
; CHECK: sll %r2, 3
; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK-DAG: sll %r2, 3
; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK: [[LABEL:\.[^:]*]]:
; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
; CHECK: nr [[ROT]], %r3
Expand Down Expand Up @@ -51,8 +51,8 @@ define i8 @f1(i8 *%src, i8 %b) {
define i8 @f2(i8 *%src) {
; CHECK-LABEL: f2:
; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
; CHECK: sll %r2, 3
; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK-DAG: sll %r2, 3
; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK: [[LABEL:\.[^:]*]]:
; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
; CHECK: nilh [[ROT]], 33023
Expand Down
8 changes: 4 additions & 4 deletions test/CodeGen/SystemZ/atomicrmw-nand-02.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -15,8 +15,8 @@
define i16 @f1(i16 *%src, i16 %b) {
; CHECK-LABEL: f1:
; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
; CHECK: sll %r2, 3
; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK-DAG: sll %r2, 3
; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK: [[LABEL:\.[^:]*]]:
; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
; CHECK: nr [[ROT]], %r3
Expand Down Expand Up @@ -51,8 +51,8 @@ define i16 @f1(i16 *%src, i16 %b) {
define i16 @f2(i16 *%src) {
; CHECK-LABEL: f2:
; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
; CHECK: sll %r2, 3
; CHECK: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK-DAG: sll %r2, 3
; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK: [[LABEL:\.[^:]*]]:
; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
; CHECK: nilh [[ROT]], 32768
Expand Down
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