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Commits on Oct 23, 2017

• [X86] Update a doxygen comment in the disassembler tablegen code. NFC

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• [X86] Fix disassembly of EVEX rounding control and SAE instructions.

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Commits on Oct 22, 2017

• [X86] More correctly support LIG and WIG for EVEX instructions in the disassembler tables.

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• [X86] Teach the disassembler that some instructions use VEX.W==0 without a corresponding VEX.W==1 instruction and we shouldn't treat them as if VEX.W is ignored.

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• [X86] Add VEX_WIG to applicable AVX512 instructions.

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• [X86] Add VEX_WIG to VROUNDSSrr/VROUNDSSrm/VROUNDSDrr/VROUNDSDrm

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• [X86] Don't allow gather/scatter to disassembler if memory operand does not use a SIB byte.

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Commits on Oct 21, 2017

• [X86] Fix disassembling of EVEX instructions to stop accidentally decoding the SIB index register as an XMM/YMM/ZMM register.

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• [ValueTracking] Remove unnecessary temporary APInt from computeNumSignBitsVectorConstant.

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• [ValueTracking] Simplify the known bits code for constant vectors a little.

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• [SelectionDAG] Don't subject ConstantSDNodes to the depth limit in computeKnownBits and ComputeNumSignBits.

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• [SelectionDAG] Don't subject ISD:Constant to the depth limit in TargetLowering::SimplifyDemandedBits.

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• [X86] Do not generate __multi3 for mul i128 on X86

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Commits on Oct 19, 2017

• [SelectionDAG] Add a check to getVectorShuffle to ensure that the only negative index we allow is -1.

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• [X86] Remove LowerEXTRACT_SUBVECTOR handler. All EXTRACT_SUBVECTORs are marked as legal.

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Commits on Oct 17, 2017

• [X86] Add masked palignr tests to vector-shuffle-masked.ll

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• [X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit.

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• [X86] Fix typo in comment. NFC

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Commits on Oct 16, 2017

• [JumpThreading] Move two PredValueInfoTy vectors to a scope closer to their usage. NFCI

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Commits on Oct 15, 2017

• [X86] Remove the SlowBTMem feature flag entirely

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• [AVX512] Don't mark EXTLOAD as legal with AVX512. Continue using custom lowering.

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• [X86] Add FeatureSlowBTMem to Haswell, Broadwell, Skylake, Cannonlake, and Knights Landing CPUs.

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• [X86] Lower vselect with constant condition to vector_shuffle even with AVX512 instructions.

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• [X86] Don't use constant condition for select instruction when testing masking ops.

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Commits on Oct 14, 2017

• [X86] Remove a bunch of dead FileCheck lines with the wrong prefix.

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• [X86] Add patterns for vzmovl+cvtpd2dq/cvttpd2dq with a load.

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• [X86] Add AVX512 versions of VCVTPD2PS to load folding tables.

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• [X86] Add patterns for vzmovl+cvtpd2ps with a load.

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• [X86] Remove some patterns for bitcasted alignednonedtemporalloads.

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• [X86] Remove unnecessary bitconverts as the root of patterns for zero extended VCVTPD2UDQZ128rr and VCVTTPD2UDQZ128rr.

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• [X86] Add additional patterns for folding loads with 128-bit VCVTDQ2PD and VCVTUDQ2PD.

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• [X86] Add AVX512 flavors of VCVTDQ2PD plus VCVTUDQ2PD to the load folding tables.

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• [X86] Remove TB_NO_REVERSE from VCVTDQ2PDYrr and VCVTPS2PDYrr in the load folding tables.

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• [X86] Add an additional isel pattern to CVTDQ2PDrm/VCVTDQ2PDrm to enable load folding without the peephole pass.

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Commits on Oct 13, 2017

• [X86] Use X86ISD::VBROADCAST in place of v2f64 X86ISD::MOVDDUP when AVX2 is available

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