Check in intermediate state, RAM still not working.

git-svn-id: svn+ssh://netzhansa.com/home/hans/cadr2-svn/trunk/secd@6 09d5f3f9-6417-0410-bd0c-e187ee50e7ab

fep/constraints.xcf

@@ -115,8 +115,8 @@ NET "ram_wen"  LOC = "G1"  ;
 #compact flash
 #NET "cf_we"	LOC = "D8";
 #NET "cf_reg"	LOC = "G5";
-#NET "cf_cs0"	LOC = "D7";
-#NET "cf_cs1"	LOC = "D5";
+NET "cf_cs0"	LOC = "D7";
+NET "cf_cs1"	LOC = "D5";
 #NET "cf_reset"	LOC = "E6";
 #NET "cf_irq"	LOC = "E4" | PULLUP;
 #NET "cf_iord"	LOC = "F4";

fep/fep_toplevel.vhd

@@ -71,7 +71,9 @@ entity secd_fep_trenz is
     cf_cd2      : in std_logic;
     iois16      : in std_logic;
     cf_oe       : out std_logic;
-    cf_pwr_en   : out std_logic
+    cf_pwr_en   : out std_logic;
+    cf_cs0      : out std_logic;
+    cf_cs1      : out std_logic
     );
 end secd_fep_trenz;
 
@@ -172,13 +174,14 @@ architecture rtl of secd_fep_trenz is
   signal blink_count  : std_logic_vector(25 downto 0) := (others => '0');
 
   -- SECD interface
-  signal secd_button      : std_logic := '0';
-  signal secd_stop        : std_logic := '1';
-  signal secd_stopped     : std_logic;
-  signal secd_state       : std_logic_vector(1 downto 0);
-  signal secd_ram_addr8   : std_logic_vector(15 downto 0) := (others => '0');
-  signal secd_ram_addr_cs : std_logic := '0';
-  signal secd_control_cs  : std_logic := '0';
+  signal secd_button           : std_logic := '0';
+  signal secd_stop             : std_logic := '1';
+  signal secd_stopped          : std_logic;
+  signal secd_state            : std_logic_vector(1 downto 0);
+  signal secd_ram_addr8        : std_logic_vector(15 downto 0) := (others => '0');
+  signal secd_ram_addr_high_cs : std_logic := '0';
+  signal secd_ram_addr_low_cs  : std_logic := '0';
+  signal secd_control_cs       : std_logic := '0';
 
   -- SECD RAM Controller interface
 
@@ -430,10 +433,12 @@ begin
     led_cs           <= '0';
     secd_ram_read8   <= '0';
     secd_ram_write8  <= '0';
-    secd_ram_addr_cs <= '0';
     secd_control_cs  <= '0';
     cpu_data_in      <= X"00";
 
+    secd_ram_addr_high_cs <= '0';
+    secd_ram_addr_low_cs  <= '0';
+
     case cpu_addr(15 downto 11) is
 
       -- Monitor ROM - $F800 - $FFFF
@@ -491,29 +496,36 @@ begin
           when "001" =>
 
             case cpu_addr(3 downto 0) is
+
               -- $E140 -> SECD Status
               when X"0" =>
                 secd_control_cs         <= cpu_vma;
                 cpu_data_in(0)          <= secd_stopped;
                 cpu_data_in(2 downto 1) <= secd_state;
 
-              -- $E141 -> SECD Address High
+              -- $E141 -> SECD Address Low
               when X"1" =>
-                secd_ram_addr_cs <= cpu_vma;
-                cpu_data_in      <= secd_ram_addr8(15 downto 8);
+                secd_ram_addr_low_cs <= cpu_vma;
+                cpu_data_in          <= secd_ram_addr8(7 downto 0);
+
+              -- $E142 -> SECD Address High
+              when X"2" =>
+                secd_ram_addr_high_cs <= cpu_vma;
+                cpu_data_in           <= secd_ram_addr8(15 downto 8);
+
+              -- $E143 -> SECD DATA
+              when X"3" =>
+                if cpu_rw = '1' then
+                  secd_ram_read8 <= cpu_vma;
+                  cpu_data_in    <= secd_ram_dout8;
+                else
+                  secd_ram_write8 <= cpu_vma;
+                end if;
 
               when others =>
                 null;
-            end case;
 
-          -- SECD Mapped Memory Page - $E2XX
-          when "010" =>
-            if cpu_rw = '1' then
-              secd_ram_read8 <= cpu_vma;
-              cpu_data_in <= secd_ram_dout8;
-            else
-              secd_ram_write8 <= cpu_vma;
-            end if;
+            end case;
 
           when others =>
             null;
@@ -616,15 +628,19 @@ begin
   --
   -- SECD RAM Adressing
   --
-  secd_ram_addressing : process(cpu_clk, secd_ram_addr_cs, cpu_rw, cpu_data_out, secd_ram_addr8)
+  secd_ram_addressing : process(cpu_clk, cpu_rw, cpu_data_out,
+                                secd_ram_addr_high_cs, secd_ram_addr_high_cs,
+                                secd_ram_addr8)
   begin
     if falling_edge(cpu_clk) then
-      secd_ram_addr8(7 downto 0) <= cpu_addr(7 downto 0);
-
-      if secd_ram_addr_cs = '1' and cpu_rw = '0' then
-        secd_ram_addr8(15 downto 8) <= cpu_data_out;
+      if cpu_rw = '0' then
+        if secd_ram_addr_high_cs = '1' then
+          secd_ram_addr8(15 downto 8) <= cpu_data_out;
+        elsif secd_ram_addr_low_cs = '1' then
+          secd_ram_addr8(7 downto 0) <= cpu_data_out;
+        end if;
       else
-        secd_ram_addr8(15 downto 8) <= secd_ram_addr8(15 downto 8);
+        secd_ram_addr8 <= secd_ram_addr8;
       end if;
     end if;
   end process;
@@ -681,5 +697,8 @@ begin
   aud_out <= (others => '0');
   int_ram_we <= not cpu_rw;
 
+  cf_cs0 <= secd_ram_read8;
+  cf_cs1 <= secd_ram_write8;
+
 end;
 

fep/secd_ram_controller.vhd

@@ -44,12 +44,12 @@ end;
 
 architecture external_ram of secd_ram_controller is
 
-  type state is (idle,
-                 read32_high, read32_low, write32_high, write32_low,
-                 read8, write8,
-                 wait_deselect);
+  type state_type is (idle,
+                      read32_high, read32_low, write32_high, write32_low,
+                      read8, write8,
+                      wait_deselect);
 
-  signal current_state, next_state: state;
+  signal state: state_type;
 
   signal selected: std_logic;
 
@@ -68,11 +68,11 @@ begin
       ram_io <= (others => 'Z');
       busy8 <= '0';
       busy32 <= '0';
-      next_state <= idle;
+      state <= idle;
 
     elsif rising_edge(clk) then
 
-      case current_state is
+      case state is
 
       when idle =>
 
@@ -95,7 +95,7 @@ begin
             ram_bhen <= '0';
           end if;
           busy8 <= '1';
-          next_state <= read8;
+          state <= read8;
 
         elsif write8_enable = '1' then
           ram_a(14 downto 0) <= addr8(15 downto 1);
@@ -108,7 +108,7 @@ begin
             ram_bhen <= '0';
           end if;
           busy8 <= '1';
-          next_state <= write8;
+          state <= write8;
 
         elsif read32_enable = '1' then
           ram_a(14 downto 1) <= addr32;
@@ -117,7 +117,7 @@ begin
           ram_cen <= '0';
           ram_oen <= '0';
           busy32 <= '1';
-          next_state <= read32_low;
+          state <= read32_low;
 
         elsif write32_enable = '1' then
           ram_a(14 downto 1) <= addr32;
@@ -126,49 +126,56 @@ begin
           ram_cen <= '0';
           ram_io(15 downto 0) <= din32(15 downto 0);
           busy32 <= '1';
-          next_state <= write32_low;
+          state <= write32_low;
         end if;
 
       when read8 =>
         if selected = '1' then
-          next_state <= wait_deselect;
+          state <= wait_deselect;
         else
-          next_state <= idle;
+          state <= idle;
         end if;
 
       when write8 =>
         if selected = '1' then
-          next_state <= wait_deselect;
+          state <= wait_deselect;
         else
-          next_state <= idle;
+          state <= idle;
         end if;
 
       when read32_low =>
         ram_a(0) <= '1';
-        next_state <= read32_high;
+        state <= read32_high;
 
       when read32_high =>
         if selected = '1' then
-          next_state <= wait_deselect;
+          state <= wait_deselect;
         else
-          next_state <= idle;
+          state <= idle;
         end if;
 
       when write32_low =>
         ram_a(0) <= '1';
-        next_state <= write32_high;
+        state <= write32_high;
 
       when write32_high =>
         ram_io(15 downto 0) <= din32(31 downto 16);
         if selected = '1' then
-          next_state <= wait_deselect;
+          state <= wait_deselect;
         else
-          next_state <= idle;
+          state <= idle;
         end if;
 
       when wait_deselect =>
+
+        ram_cen <= '1';
+        ram_oen <= '1';
+        ram_blen <= '1';
+        ram_bhen <= '1';
+        ram_io <= (others => 'Z');
+
         if selected = '0' then
-          next_state <= idle;
+          state <= idle;
         end if;
       end case;
     end if;
@@ -183,22 +190,13 @@ begin
     end if;
   end process;
 
-  process_next_state : process(clk, reset, next_state)
-  begin
-    if reset = '1' then
-      current_state <= idle;
-    else
-      current_state <= next_state;
-    end if;
-  end process;
-
-  process_port : process(clk, ram_io, current_state)
+  process_port : process(clk, ram_io, state)
   begin
     if falling_edge(clk) then
 
       ram_wen <= '1';
 
-      case current_state is
+      case state is
 
         when read8 =>
           if addr8(0) = '0' then

fep/secd_ram_controller_TB.vhd

@@ -168,6 +168,7 @@ begin
       addr8 <= addr;
       read8_enable <= '1';
       wait until busy8 = '1';
+      wait for 10 ns;
       read8_enable <= '0';
       wait until busy8 = '0';
       result := din8;
@@ -180,6 +181,7 @@ begin
       din8 <= data;
       write8_enable <= '1';
       wait until busy8 = '1';
+      wait for 10 ns;
       write8_enable <= '0';
       wait until busy8 = '0';
     end procedure;
@@ -191,6 +193,7 @@ begin
       addr32 <= addr(13 downto 0);
       read32_enable <= '1';
       wait until busy32 = '1';
+      wait for 10 ns;
       read32_enable <= '0';
       wait until busy32 = '0';
       result := din32;
@@ -204,6 +207,7 @@ begin
       din32 <= data;
       write32_enable <= '1';
       wait until busy32 = '1';
+      wait for 10 ns;
       write32_enable <= '0';
       wait until busy32 = '0';
     end procedure;