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Rename RV128 shamt to shamtq
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This will reduce the chance that people pick the wrong shamt width.
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aswaterman committed Jan 12, 2023
1 parent c190e55 commit e961083
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Showing 2 changed files with 5 additions and 4 deletions.
3 changes: 2 additions & 1 deletion constants.py
Original file line number Diff line number Diff line change
Expand Up @@ -494,7 +494,7 @@
arg_lut['imm12lo'] = (11, 7)
arg_lut['bimm12lo'] = (11, 7)
arg_lut['zimm'] = (19, 15)
arg_lut['shamt'] = (26, 20)
arg_lut['shamtq'] = (26, 20)
arg_lut['shamtw'] = (24, 20)
arg_lut['shamtw4'] = (23, 20)
arg_lut['shamtd'] = (25, 20)
Expand Down Expand Up @@ -592,6 +592,7 @@
latex_mapping['zimm'] = 'uimm'
latex_mapping['shamtw'] = 'shamt'
latex_mapping['shamtd'] = 'shamt'
latex_mapping['shamtq'] = 'shamt'
latex_mapping['rd_p'] = "rd\\,$'$"
latex_mapping['rs1_p'] = "rs1\\,$'$"
latex_mapping['rs2_p'] = "rs2\\,$'$"
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6 changes: 3 additions & 3 deletions unratified/rv128_i
Original file line number Diff line number Diff line change
Expand Up @@ -17,6 +17,6 @@ ldu rd rs1 imm12 14..12=7 6..2=0x00 1..0=3
sq imm12hi rs1 rs2 imm12lo 14..12=4 6..2=0x08 1..0=3

# RV32 and RV64 versions of these are in opcodes-pseudo
slli rd rs1 31..27=0 shamt 14..12=1 6..2=0x04 1..0=3
srli rd rs1 31..27=0 shamt 14..12=5 6..2=0x04 1..0=3
srai rd rs1 31..27=8 shamt 14..12=5 6..2=0x04 1..0=3
slli rd rs1 31..27=0 shamtq 14..12=1 6..2=0x04 1..0=3
srli rd rs1 31..27=0 shamtq 14..12=5 6..2=0x04 1..0=3
srai rd rs1 31..27=8 shamtq 14..12=5 6..2=0x04 1..0=3

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