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g12b: ddr: sync ddr driver with g12a [3/3]
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PD#165090

Problem:
need sync latest ddr code

Solution:
sync code with g12a

Verify:
test pass on g12b skt board

Change-Id: Id49b9d2578ff68293b8959302ef334c13812d57c
Signed-off-by: xiaobo gu <[email protected]>
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xiaobo gu committed Jun 25, 2018
1 parent 0f48a8e commit 51a37bc
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Showing 2 changed files with 72 additions and 78 deletions.
57 changes: 0 additions & 57 deletions arch/arm/include/asm/arch-g12b/timing.h
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Original file line number Diff line number Diff line change
Expand Up @@ -229,63 +229,6 @@ typedef struct ddr_set{
/* v2 start */
}__attribute__ ((packed)) ddr_set_t;

typedef struct ddr_timing{
//Identifier
unsigned char identifier;

//DTPR0
unsigned char cfg_ddr_rtp;
unsigned char cfg_ddr_wtr;
unsigned char cfg_ddr_rp;
unsigned char cfg_ddr_rcd;
unsigned char cfg_ddr_ras;
unsigned char cfg_ddr_rrd;
unsigned char cfg_ddr_rc;

//DTPR1
unsigned char cfg_ddr_mrd;
unsigned char cfg_ddr_mod;
unsigned char cfg_ddr_faw;
unsigned char cfg_ddr_wlmrd;
unsigned char cfg_ddr_wlo;

//DTPR2
unsigned char cfg_ddr_xp;

//DTPR1
unsigned short cfg_ddr_rfc;

//DTPR2
unsigned short cfg_ddr_xs;
unsigned short cfg_ddr_dllk;
unsigned char cfg_ddr_cke;
unsigned char cfg_ddr_rtodt;
unsigned char cfg_ddr_rtw;

unsigned char cfg_ddr_refi;
unsigned char cfg_ddr_refi_mddr3;
unsigned char cfg_ddr_cl;
unsigned char cfg_ddr_wr;
unsigned char cfg_ddr_cwl;
unsigned char cfg_ddr_al;
unsigned char cfg_ddr_dqs;
unsigned char cfg_ddr_cksre;
unsigned char cfg_ddr_cksrx;
unsigned char cfg_ddr_zqcs;
unsigned char cfg_ddr_xpdll;
unsigned short cfg_ddr_exsr;
unsigned short cfg_ddr_zqcl;
unsigned short cfg_ddr_zqcsi;

unsigned char cfg_ddr_tccdl;
unsigned char cfg_ddr_tdqsck;
unsigned char cfg_ddr_tdqsckmax;
unsigned char rsv_char;

/* reserved */
unsigned int rsv_int;
}__attribute__ ((packed)) ddr_timing_t;

typedef struct pll_set{
unsigned short cpu_clk;
unsigned short pxp;
Expand Down
93 changes: 72 additions & 21 deletions board/amlogic/g12b_skt_v1/firmware/timing.c
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Original file line number Diff line number Diff line change
Expand Up @@ -98,16 +98,15 @@ ddr_set_t __ddr_setting[] = {
.dfi_odt_config = 0x0808,
.PllBypassEn = 0, //bit0-ps0,bit1-ps1
.ddr_rdbi_wr_enable = 0,
.pll_ssc_mode = 0,
.clk_drv_ohm = 40,
.cs_drv_ohm = 40,
.ac_drv_ohm = 40,
.soc_data_drv_ohm_p = 34,
.soc_data_drv_ohm_n = 34,
.soc_data_drv_ohm_p = 40,
.soc_data_drv_ohm_n = 40,
.soc_data_odt_ohm_p = 60,
.soc_data_odt_ohm_n = 0,
.dram_data_drv_ohm = 48, //34, //ddr4 sdram only 34 or 48, skt board use 34 better
.dram_data_odt_ohm = 60,
.dram_data_drv_ohm = 34,//48, //34, //ddr4 sdram only 34 or 48, skt board use 34 better
.dram_data_odt_ohm = 60, //60,
.dram_ac_odt_ohm = 0,
.soc_clk_slew_rate = 0x3ff,
.soc_cs_slew_rate = 0x3ff,
Expand All @@ -117,8 +116,8 @@ ddr_set_t __ddr_setting[] = {
.vref_receiver_permil = 700,
.vref_dram_permil = 700,
.vref_reverse = 0,
.ac_trace_delay = {00,00},
.ac_pinmux = {00,00},
//.ac_trace_delay ={0x0,0x0},// {0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40},
.ac_trace_delay = {0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40},
.ddr_dmc_remap = {
[0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),
[1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
Expand All @@ -142,7 +141,7 @@ ddr_set_t __ddr_setting[] = {
* 2. config 3000ppm down ss. then mode=2, strength=6
* .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
*/
.pll_ssc_mode = 0,
.pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm,
.ddr_func = DDR_FUNC,
.magic = DRAM_CFG_MAGIC,
},
Expand All @@ -164,11 +163,11 @@ ddr_set_t __ddr_setting[] = {
.dram_cs0_size_MB = 1024,
.dram_cs1_size_MB = 1024,
.training_SequenceCtrl = {0x31f,0}, //ddr3 0x21f 0x31f
.phy_odt_config_rank = {30,30,30,30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
.dfi_odt_config = 0x0808,
.phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
.dfi_odt_config = 0x0c0c,
.PllBypassEn = 0, //bit0-ps0,bit1-ps1
.ddr_rdbi_wr_enable = 0,
.pll_ssc_mode = 0,
.pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
.clk_drv_ohm = 40,
.cs_drv_ohm = 40,
.ac_drv_ohm = 40,
Expand All @@ -187,19 +186,44 @@ ddr_set_t __ddr_setting[] = {
.vref_receiver_permil = 500, //700,
.vref_dram_permil = 500, //700,
.vref_reverse = 0,
.ac_trace_delay = {00,00},
.ac_trace_delay = {0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40},
//{00,00},
.ac_pinmux = {00,00},
#if 1
.ddr_dmc_remap = {
[0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),
[1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
[2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
[3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
[4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ),
},
#else
//16bit
.ddr_dmc_remap = {
[0] = ( 0 | 5 << 5 | 6<< 10 | 7 << 15 | 8 << 20 | 9 << 25 ),
[1] = ( 10| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
[2] = ( 17|( 18 << 5) |( 19 << 10) |( 20< 15) |( 21 << 20) | (22 << 25 )),
[3] = ( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 28 << 25 ),
[4] = ( 29| 11<< 5 | 12 << 10 | 13<< 15 | 0 << 20 | 0 << 25 ),
},
#endif
.ddr_lpddr34_ca_remap = {00,00},
.ddr_lpddr34_dq_remap = {00,00},
.dram_rtt_nom_wr_park = {00,00},

/* pll ssc config:
*
* pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
* ppm = strength * 500
* mode: 0=center, 1=up, 2=down
*
* eg:
* 1. config 1000ppm center ss. then mode=0, strength=2
* .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
* 2. config 3000ppm down ss. then mode=2, strength=6
* .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
*/
.pll_ssc_mode = 0,
.ddr_func = DDR_FUNC,
.magic = DRAM_CFG_MAGIC,
},
Expand Down Expand Up @@ -227,7 +251,7 @@ ddr_set_t __ddr_setting[] = {
.dfi_odt_config = 0x0808,
.PllBypassEn = 0, //bit0-ps0,bit1-ps1
.ddr_rdbi_wr_enable = 0,
.pll_ssc_mode = 0,
.pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
.clk_drv_ohm = 40,
.cs_drv_ohm = 40,
.ac_drv_ohm = 40,
Expand All @@ -238,9 +262,9 @@ ddr_set_t __ddr_setting[] = {
.dram_data_drv_ohm = 40, //lpddr4 sdram only240/1-6
.dram_data_odt_ohm = 120,
.dram_ac_odt_ohm = 120,
.soc_clk_slew_rate = 0x3ff,//0x253,
.soc_cs_slew_rate = 0x100,//0x253,
.soc_ac_slew_rate = 0x100,//0x253,
.soc_clk_slew_rate = 0x3ff,//0x253,
.soc_cs_slew_rate = 0x100,//0x253,
.soc_ac_slew_rate = 0x100,//0x253,
.soc_data_slew_rate = 0x1ff,
.vref_output_permil = 350,//200,
.vref_receiver_permil = 200,
Expand All @@ -256,8 +280,22 @@ ddr_set_t __ddr_setting[] = {
[4] = ( 30| 12 << 5 | 13 << 10 | 14<< 15 | 0 << 20 | 0 << 25 ),
},
.ddr_lpddr34_ca_remap = {00,00},
.ddr_lpddr34_dq_remap = {00,00},
.ddr_lpddr34_dq_remap = {3,2,0,1,7,6,5,4,14,13,12,15,8,9,11,10,20,21,22,23,16,17,19,18,24,25,28,26,31,30,27,29},
.dram_rtt_nom_wr_park = {00,00},

/* pll ssc config:
*
* pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
* ppm = strength * 500
* mode: 0=center, 1=up, 2=down
*
* eg:
* 1. config 1000ppm center ss. then mode=0, strength=2
* .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
* 2. config 3000ppm down ss. then mode=2, strength=6
* .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
*/
.pll_ssc_mode = 0,
.ddr_func = DDR_FUNC,
.magic = DRAM_CFG_MAGIC,
.diagnose = CONFIG_DIAGNOSE_DISABLE,
Expand Down Expand Up @@ -286,7 +324,7 @@ ddr_set_t __ddr_setting[] = {
.dfi_odt_config = 0x0808,
.PllBypassEn = 0, //bit0-ps0,bit1-ps1
.ddr_rdbi_wr_enable = 0,
.pll_ssc_mode = 0,
.pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
.clk_drv_ohm = 40,
.cs_drv_ohm = 40,
.ac_drv_ohm = 40,
Expand All @@ -297,9 +335,9 @@ ddr_set_t __ddr_setting[] = {
.dram_data_drv_ohm = 40, //lpddr4 sdram only240/1-6
.dram_data_odt_ohm = 120,
.dram_ac_odt_ohm = 120,
.soc_clk_slew_rate = 0x3ff,//0x253,
.soc_cs_slew_rate = 0x100,//0x253,
.soc_ac_slew_rate = 0x100,//0x253,
.soc_clk_slew_rate = 0x3ff,//0x253,
.soc_cs_slew_rate = 0x100,//0x253,
.soc_ac_slew_rate = 0x100,//0x253,
.soc_data_slew_rate = 0x1ff,
.vref_output_permil = 350,//200,
.vref_receiver_permil = 200,
Expand All @@ -317,6 +355,19 @@ ddr_set_t __ddr_setting[] = {
.ddr_lpddr34_ca_remap = {00,00},
.ddr_lpddr34_dq_remap = {00,00},
.dram_rtt_nom_wr_park = {00,00},
/* pll ssc config:
*
* pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
* ppm = strength * 500
* mode: 0=center, 1=up, 2=down
*
* eg:
* 1. config 1000ppm center ss. then mode=0, strength=2
* .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
* 2. config 3000ppm down ss. then mode=2, strength=6
* .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
*/
.pll_ssc_mode = 0,
.ddr_func = DDR_FUNC,
.magic = DRAM_CFG_MAGIC,
},
Expand Down

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