ODROID-C3: introduce odroid-c3 board and configuration

Change-Id: I0cdbde1fd6f508b9939c5aea5ee72450be467c91

arch/arm/cpu/armv8/g12a/firmware/scp_task/suspend.c

@@ -26,7 +26,9 @@
 unsigned int time;
 #include <scp_remote.c>
 
+#ifdef CONFIG_ADC_KEY
 #include <scp_adc.c>
+#endif
 #include <pwr_ctrl.c>
 #include <hdmi_cec_arc.c>
 

board/amlogic/Kconfig

@@ -190,6 +190,10 @@ config ODROID_C2
 	bool "Support Hardkernel ODROID-C2 board"
 	default n
 
+config ODROID_C3
+	bool "Support Hardkernel ODROID-C3 board"
+	default n
+
 if GXB_SKT_V1
 source "board/amlogic/gxb_skt_v1/Kconfig"
 endif
@@ -373,3 +377,7 @@ endif
 if ODROID_C2
 source "board/hardkernel/odroidc2/Kconfig"
 endif
+
+if ODROID_C3
+source "board/hardkernel/odroidc3/Kconfig"
+endif

board/hardkernel/odroidc3/Kconfig

@@ -0,0 +1,22 @@
+if TARGET_MESON_G12A
+
+config SYS_CPU
+	string
+	default "armv8"
+
+config SYS_BOARD
+	string
+	default "odroidc3"
+
+config SYS_VENDOR
+	string
+	default "hardkernel"
+
+config SYS_SOC
+	string
+	default "g12a"
+
+config SYS_CONFIG_NAME
+	default "odroidc3"
+
+endif

board/hardkernel/odroidc3/Makefile

@@ -0,0 +1,2 @@
+obj-y += $(BOARD).o eth_setup.o
+obj-$(CONFIG_AML_LCD) += lcd.o

board/hardkernel/odroidc3/eth_setup.c

@@ -0,0 +1,46 @@
+/*
+ * board/hardkernel/odroidc3/eth_setup.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <asm/arch/eth_setup.h>
+/*
+ * setup eth device board socket
+ */
+struct eth_board_socket* eth_board_setup(char *name){
+	struct eth_board_socket* new_board;
+	new_board= (struct eth_board_socket*) malloc(sizeof(struct eth_board_socket));
+	if (NULL == new_board) return NULL;
+	if (name != NULL) {
+		new_board->name=(char*)malloc(strlen(name));
+		strncpy(new_board->name,name,strlen(name));
+	}else{
+		new_board->name="gxb";
+	}
+
+	new_board->eth_pinmux_setup=NULL ;
+	new_board->eth_clock_configure=NULL;
+	new_board->eth_hw_reset=NULL;
+	return new_board;
+}

board/hardkernel/odroidc3/firmware/scp_task/pwm_ctrl.h

@@ -0,0 +1,40 @@
+/*
+ * board/hardkernel/odroidc3/firmware/scp_task/pwr_ctrl.h
+ * table for Dynamic Voltage/Frequency Scaling
+ */
+#ifndef __PWM_CTRL_H__
+#define __PWM_CTRL_H__
+
+static int pwm_voltage_table_ee[][2] = {
+	{ 0x1c0000,  681},
+	{ 0x1b0001,  691},
+	{ 0x1a0002,  701},
+	{ 0x190003,  711},
+	{ 0x180004,  721},
+	{ 0x170005,  731},
+	{ 0x160006,  741},
+	{ 0x150007,  751},
+	{ 0x140008,  761},
+	{ 0x130009,  772},
+	{ 0x12000a,  782},
+	{ 0x11000b,  792},
+	{ 0x10000c,  802},
+	{ 0x0f000d,  812},
+	{ 0x0e000e,  822},
+	{ 0x0d000f,  832},
+	{ 0x0c0010,  842},
+	{ 0x0b0011,  852},
+	{ 0x0a0012,  862},
+	{ 0x090013,  872},
+	{ 0x080014,  882},
+	{ 0x070015,  892},
+	{ 0x060016,  902},
+	{ 0x050017,  912},
+	{ 0x040018,  922},
+	{ 0x030019,  932},
+	{ 0x02001a,  942},
+	{ 0x01001b,  952},
+	{ 0x00001c,  962}
+};
+
+#endif //__PWM_CTRL_H__

board/hardkernel/odroidc3/firmware/scp_task/pwr_ctrl.c

@@ -0,0 +1,179 @@
+/*
+ * board/hardkernel/odroidc3/firmware/scp_task/pwr_ctrl.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+*/
+
+#include <gpio.h>
+#include "pwm_ctrl.h"
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+static void set_vddee_voltage(unsigned int target_voltage)
+{
+	unsigned int to;
+
+	for (to = 0; to < ARRAY_SIZE(pwm_voltage_table_ee); to++) {
+		if (pwm_voltage_table_ee[to][1] >= target_voltage) {
+			break;
+		}
+	}
+
+	if (to >= ARRAY_SIZE(pwm_voltage_table_ee)) {
+		to = ARRAY_SIZE(pwm_voltage_table_ee) - 1;
+	}
+
+	writel(pwm_voltage_table_ee[to][0],AO_PWM_PWM_B);
+}
+
+static void power_off_at_24M(unsigned int suspend_from)
+{
+	/*set gpioH_8 low to power off vcc 5v*/
+	writel(readl(PREG_PAD_GPIO3_EN_N) & (~(1 << 8)), PREG_PAD_GPIO3_EN_N);
+	writel(readl(PERIPHS_PIN_MUX_C) & (~(0xf)), PERIPHS_PIN_MUX_C);
+
+	/*set test_n low to power off vcck & vcc 3.3v*/
+	writel(readl(AO_GPIO_O) & (~(1 << 31)), AO_GPIO_O);
+	writel(readl(AO_GPIO_O_EN_N) & (~(1 << 31)), AO_GPIO_O_EN_N);
+	writel(readl(AO_RTI_PIN_MUX_REG1) & (~(0xf << 28)), AO_RTI_PIN_MUX_REG1);
+
+	/*step down ee voltage*/
+	set_vddee_voltage(CONFIG_VDDEE_SLEEP_VOLTAGE);
+}
+
+static void power_on_at_24M(unsigned int suspend_from)
+{
+	/*step up ee voltage*/
+	set_vddee_voltage(CONFIG_VDDEE_INIT_VOLTAGE);
+
+	/*set test_n low to power on vcck & vcc 3.3v*/
+	writel(readl(AO_GPIO_O) | (1 << 31), AO_GPIO_O);
+	writel(readl(AO_GPIO_O_EN_N) & (~(1 << 31)), AO_GPIO_O_EN_N);
+	writel(readl(AO_RTI_PIN_MUX_REG1) & (~(0xf << 28)), AO_RTI_PIN_MUX_REG1);
+	_udelay(100);
+
+	/*set gpioH_8 low to power on vcc 5v*/
+	writel(readl(PREG_PAD_GPIO3_EN_N) | (1 << 8), PREG_PAD_GPIO3_EN_N);
+	writel(readl(PERIPHS_PIN_MUX_C) & (~(0xf)), PERIPHS_PIN_MUX_C);
+	_udelay(10000);
+}
+
+void get_wakeup_source(void *response, unsigned int suspend_from)
+{
+	struct wakeup_info *p = (struct wakeup_info *)response;
+	struct wakeup_gpio_info *gpio;
+	unsigned val;
+	unsigned i = 0;
+
+	p->status = RESPONSE_OK;
+	val = (POWER_KEY_WAKEUP_SRC | AUTO_WAKEUP_SRC | REMOTE_WAKEUP_SRC |
+	       ETH_PHY_WAKEUP_SRC | BT_WAKEUP_SRC | ETH_PHY_GPIO_SRC);
+
+	p->sources = val;
+
+	/* Power Key: AO_GPIO[3]*/
+	gpio = &(p->gpio_info[i]);
+	gpio->wakeup_id = POWER_KEY_WAKEUP_SRC;
+	gpio->gpio_in_idx = GPIOAO_3;
+	gpio->gpio_in_ao = 1;
+	gpio->gpio_out_idx = -1;
+	gpio->gpio_out_ao = -1;
+	gpio->irq = IRQ_AO_GPIO0_NUM;
+	gpio->trig_type = GPIO_IRQ_FALLING_EDGE;
+	p->gpio_info_count = ++i;
+
+	/*Eth:GPIOZ_14*/
+	gpio = &(p->gpio_info[i]);
+	gpio->wakeup_id = ETH_PHY_GPIO_SRC;
+	gpio->gpio_in_idx = GPIOZ_14;
+	gpio->gpio_in_ao = 0;
+	gpio->gpio_out_idx = -1;
+	gpio->gpio_out_ao = -1;
+	gpio->irq = IRQ_GPIO1_NUM;
+	gpio->trig_type = GPIO_IRQ_FALLING_EDGE;
+	p->gpio_info_count = ++i;
+
+}
+extern void __switch_idle_task(void);
+
+static unsigned int detect_key(unsigned int suspend_from)
+{
+	int exit_reason = 0;
+	unsigned *irq = (unsigned *)WAKEUP_SRC_IRQ_ADDR_BASE;
+#ifdef CONFIG_ADC_KEY
+	unsigned char adc_key_cnt = 0;
+	saradc_enable();
+#endif
+	init_remote();
+
+	do {
+		if (irq[IRQ_AO_IR_DEC] == IRQ_AO_IR_DEC_NUM) {
+			irq[IRQ_AO_IR_DEC] = 0xFFFFFFFF;
+			if (remote_detect_key())
+				exit_reason = REMOTE_WAKEUP;
+		}
+
+#ifdef CONFIG_ADC_KEY
+		if (irq[IRQ_AO_TIMERA] == IRQ_AO_TIMERA_NUM) {
+			irq[IRQ_AO_TIMERA] = 0xFFFFFFFF;
+			if (check_adc_key_resume()) {
+				adc_key_cnt++;
+				/*using variable 'adc_key_cnt' to eliminate the dithering of the key*/
+				if (2 == adc_key_cnt)
+					exit_reason = POWER_KEY_WAKEUP;
+			} else {
+				adc_key_cnt = 0;
+			}
+		}
+#endif
+
+#ifdef CONFIG_GPIO_POWER_KEY
+		if (irq[IRQ_AO_GPIO0] == IRQ_AO_GPIO0_NUM) {
+			irq[IRQ_AO_GPIO0] = 0xFFFFFFFF;
+			if ((readl(AO_GPIO_I) & (1<<3)) == 0)
+				exit_reason = POWER_KEY_WAKEUP;
+		}
+#endif
+
+#if 0
+		if (irq[IRQ_GPIO1] == IRQ_GPIO1_NUM) {
+			irq[IRQ_GPIO1] = 0xFFFFFFFF;
+			if (!(readl(PREG_PAD_GPIO4_I) & (0x01 << 14))
+					&& (readl(PREG_PAD_GPIO4_EN_N) & (0x01 << 14)))
+				exit_reason = ETH_PHY_GPIO;
+		}
+#endif
+		if (exit_reason)
+			break;
+		else
+			__switch_idle_task();
+	} while (1);
+
+#ifdef CONFIG_ADC_KEY
+	saradc_disable();
+#endif
+
+	return exit_reason;
+}
+
+static void pwr_op_init(struct pwr_op *pwr_op)
+{
+	pwr_op->power_off_at_24M = power_off_at_24M;
+	pwr_op->power_on_at_24M = power_on_at_24M;
+	pwr_op->detect_key = detect_key;
+	pwr_op->get_wakeup_source = get_wakeup_source;
+}