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fix all the code in other non-X86 archs after the change made by commit
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5329a6f
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@aquynh
aquynh committed Jun 9, 2014
1 parent 12f93cb commit 29fd0f6
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Showing 8 changed files with 592 additions and 644 deletions.
52 changes: 0 additions & 52 deletions MCInst.h
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Original file line number Diff line number Diff line change
Expand Up @@ -85,58 +85,6 @@ void MCOperand_CreateReg0(MCInst *inst, unsigned Reg);

void MCOperand_CreateImm0(MCInst *inst, int64_t Val);

// NOTE: this structure is a flatten version of cs_insn struct
// Detail information of disassembled instruction
typedef struct cs_insn_flat {
// Instruction ID
// Find the instruction id from header file of corresponding architecture,
// such as arm.h for ARM, x86.h for X86, etc...
// This information is available even when CS_OPT_DETAIL = CS_OPT_OFF
unsigned int id;

// Address (EIP) of this instruction
// This information is available even when CS_OPT_DETAIL = CS_OPT_OFF
uint64_t address;

// Size of this instruction
// This information is available even when CS_OPT_DETAIL = CS_OPT_OFF
uint16_t size;
// Machine bytes of this instruction, with number of bytes indicated by @size above
// This information is available even when CS_OPT_DETAIL = CS_OPT_OFF
uint8_t bytes[16];

// Ascii text of instruction mnemonic
// This information is available even when CS_OPT_DETAIL = CS_OPT_OFF
char mnemonic[32];

// Ascii text of instruction operands
// This information is available even when CS_OPT_DETAIL = CS_OPT_OFF
char op_str[160];

// NOTE: All information below is not available when CS_OPT_DETAIL = CS_OPT_OFF

uint8_t regs_read[12]; // list of implicit registers read by this insn
uint8_t regs_read_count; // number of implicit registers read by this insn

uint8_t regs_write[20]; // list of implicit registers modified by this insn
uint8_t regs_write_count; // number of implicit registers modified by this insn

uint8_t groups[8]; // list of group this instruction belong to
uint8_t groups_count; // number of groups this insn belongs to

// Architecture-specific instruction info
union {
cs_x86 x86; // X86 architecture, including 16-bit, 32-bit & 64-bit mode
cs_arm64 arm64; // ARM64 architecture (aka AArch64)
cs_arm arm; // ARM architecture (including Thumb/Thumb2)
cs_mips mips; // MIPS architecture
cs_ppc ppc; // PowerPC architecture
cs_sparc sparc; // Sparc architecture
cs_sysz sysz; // SystemZ architecture
cs_xcore xcore; // XCore architecture
};
} cs_insn_flat;

/// MCInst - Instances of this class represent a single low-level machine
/// instruction.
struct MCInst {
Expand Down
196 changes: 98 additions & 98 deletions arch/AArch64/AArch64InstPrinter.c
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674 changes: 337 additions & 337 deletions arch/ARM/ARMInstPrinter.c
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36 changes: 18 additions & 18 deletions arch/Mips/MipsInstPrinter.c
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Original file line number Diff line number Diff line change
Expand Up @@ -93,12 +93,12 @@ static void set_mem_access(MCInst *MI, bool status)
return;

if (status) {
MI->flat_insn.mips.operands[MI->flat_insn.mips.op_count].type = MIPS_OP_MEM;
MI->flat_insn.mips.operands[MI->flat_insn.mips.op_count].mem.base = MIPS_REG_INVALID;
MI->flat_insn.mips.operands[MI->flat_insn.mips.op_count].mem.disp = 0;
MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_MEM;
MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].mem.base = MIPS_REG_INVALID;
MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].mem.disp = 0;
} else {
// done, create the next operand slot
MI->flat_insn.mips.op_count++;
MI->flat_insn->detail->mips.op_count++;
}
}

Expand Down Expand Up @@ -230,11 +230,11 @@ static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
reg = Mips_map_register(reg);
if (MI->csh->detail) {
if (MI->csh->doing_mem) {
MI->flat_insn.mips.operands[MI->flat_insn.mips.op_count].mem.base = reg;
MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].mem.base = reg;
} else {
MI->flat_insn.mips.operands[MI->flat_insn.mips.op_count].type = MIPS_OP_REG;
MI->flat_insn.mips.operands[MI->flat_insn.mips.op_count].reg = reg;
MI->flat_insn.mips.op_count++;
MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_REG;
MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].reg = reg;
MI->flat_insn->detail->mips.op_count++;
}
}
}
Expand All @@ -256,7 +256,7 @@ static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
}
}
if (MI->csh->detail)
MI->flat_insn.mips.operands[MI->flat_insn.mips.op_count].mem.disp = imm;
MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].mem.disp = imm;
} else {
if (imm >= 0) {
if (imm > HEX_THRESHOLD)
Expand All @@ -271,9 +271,9 @@ static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
}

if (MI->csh->detail) {
MI->flat_insn.mips.operands[MI->flat_insn.mips.op_count].type = MIPS_OP_IMM;
MI->flat_insn.mips.operands[MI->flat_insn.mips.op_count].imm = imm;
MI->flat_insn.mips.op_count++;
MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_IMM;
MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].imm = imm;
MI->flat_insn->detail->mips.op_count++;
}
}
}
Expand All @@ -296,9 +296,9 @@ static void printUnsignedImm(MCInst *MI, int opNum, SStream *O)
SStream_concat(O, "-%u", (short int)-imm);
}
if (MI->csh->detail) {
MI->flat_insn.mips.operands[MI->flat_insn.mips.op_count].type = MIPS_OP_IMM;
MI->flat_insn.mips.operands[MI->flat_insn.mips.op_count].imm = (unsigned short int)imm;
MI->flat_insn.mips.op_count++;
MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_IMM;
MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].imm = (unsigned short int)imm;
MI->flat_insn->detail->mips.op_count++;
}
} else
printOperand(MI, opNum, O);
Expand All @@ -314,9 +314,9 @@ static void printUnsignedImm8(MCInst *MI, int opNum, SStream *O)
else
SStream_concat(O, "%u", imm);
if (MI->csh->detail) {
MI->flat_insn.mips.operands[MI->flat_insn.mips.op_count].type = MIPS_OP_IMM;
MI->flat_insn.mips.operands[MI->flat_insn.mips.op_count].imm = imm;
MI->flat_insn.mips.op_count++;
MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_IMM;
MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].imm = imm;
MI->flat_insn->detail->mips.op_count++;
}
} else
printOperand(MI, opNum, O);
Expand Down
64 changes: 32 additions & 32 deletions arch/PowerPC/PPCInstPrinter.c
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Original file line number Diff line number Diff line change
Expand Up @@ -45,12 +45,12 @@ static void set_mem_access(MCInst *MI, bool status)
MI->csh->doing_mem = status;

if (status) {
MI->flat_insn.ppc.operands[MI->flat_insn.ppc.op_count].type = PPC_OP_MEM;
MI->flat_insn.ppc.operands[MI->flat_insn.ppc.op_count].mem.base = PPC_REG_INVALID;
MI->flat_insn.ppc.operands[MI->flat_insn.ppc.op_count].mem.disp = 0;
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_MEM;
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].mem.base = PPC_REG_INVALID;
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].mem.disp = 0;
} else {
// done, create the next operand slot
MI->flat_insn.ppc.op_count++;
MI->flat_insn->detail->ppc.op_count++;
}
}

Expand Down Expand Up @@ -139,7 +139,7 @@ static void printPredicateOperand(MCInst *MI, unsigned OpNo,
{
unsigned Code = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNo));

MI->flat_insn.ppc.bc = (ppc_bc)Code;
MI->flat_insn->detail->ppc.bc = (ppc_bc)Code;

if (!strcmp(Modifier, "cc")) {
switch ((ppc_predicate)Code) {
Expand Down Expand Up @@ -247,9 +247,9 @@ static void printS5ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
}

if (MI->csh->detail) {
MI->flat_insn.ppc.operands[MI->flat_insn.ppc.op_count].type = PPC_OP_IMM;
MI->flat_insn.ppc.operands[MI->flat_insn.ppc.op_count].imm = Value;
MI->flat_insn.ppc.op_count++;
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Value;
MI->flat_insn->detail->ppc.op_count++;
}
}

Expand All @@ -263,9 +263,9 @@ static void printU5ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
SStream_concat(O, "%u", Value);

if (MI->csh->detail) {
MI->flat_insn.ppc.operands[MI->flat_insn.ppc.op_count].type = PPC_OP_IMM;
MI->flat_insn.ppc.operands[MI->flat_insn.ppc.op_count].imm = Value;
MI->flat_insn.ppc.op_count++;
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Value;
MI->flat_insn->detail->ppc.op_count++;
}
}

Expand All @@ -279,9 +279,9 @@ static void printU6ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
SStream_concat(O, "%u", Value);

if (MI->csh->detail) {
MI->flat_insn.ppc.operands[MI->flat_insn.ppc.op_count].type = PPC_OP_IMM;
MI->flat_insn.ppc.operands[MI->flat_insn.ppc.op_count].imm = Value;
MI->flat_insn.ppc.op_count++;
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Value;
MI->flat_insn->detail->ppc.op_count++;
}
}

Expand All @@ -302,9 +302,9 @@ static void printS16ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
}

if (MI->csh->detail) {
MI->flat_insn.ppc.operands[MI->flat_insn.ppc.op_count].type = PPC_OP_IMM;
MI->flat_insn.ppc.operands[MI->flat_insn.ppc.op_count].imm = Imm;
MI->flat_insn.ppc.op_count++;
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Imm;
MI->flat_insn->detail->ppc.op_count++;
}
} else
printOperand(MI, OpNo, O);
Expand Down Expand Up @@ -332,11 +332,11 @@ static void printS16ImmOperand_Mem(MCInst *MI, unsigned OpNo, SStream *O)

if (MI->csh->detail) {
if (MI->csh->doing_mem) {
MI->flat_insn.ppc.operands[MI->flat_insn.ppc.op_count].mem.disp = Imm;
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].mem.disp = Imm;
} else {
MI->flat_insn.ppc.operands[MI->flat_insn.ppc.op_count].type = PPC_OP_IMM;
MI->flat_insn.ppc.operands[MI->flat_insn.ppc.op_count].imm = Imm;
MI->flat_insn.ppc.op_count++;
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Imm;
MI->flat_insn->detail->ppc.op_count++;
}
}
} else
Expand All @@ -353,9 +353,9 @@ static void printU16ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
SStream_concat(O, "%u", Imm);

if (MI->csh->detail) {
MI->flat_insn.ppc.operands[MI->flat_insn.ppc.op_count].type = PPC_OP_IMM;
MI->flat_insn.ppc.operands[MI->flat_insn.ppc.op_count].imm = Imm;
MI->flat_insn.ppc.op_count++;
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Imm;
MI->flat_insn->detail->ppc.op_count++;
}
} else
printOperand(MI, OpNo, O);
Expand Down Expand Up @@ -504,11 +504,11 @@ static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)

if (MI->csh->detail) {
if (MI->csh->doing_mem) {
MI->flat_insn.ppc.operands[MI->flat_insn.ppc.op_count].mem.base = reg;
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].mem.base = reg;
} else {
MI->flat_insn.ppc.operands[MI->flat_insn.ppc.op_count].type = PPC_OP_REG;
MI->flat_insn.ppc.operands[MI->flat_insn.ppc.op_count].reg = reg;
MI->flat_insn.ppc.op_count++;
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_REG;
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].reg = reg;
MI->flat_insn->detail->ppc.op_count++;
}
}

Expand All @@ -531,11 +531,11 @@ static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)

if (MI->csh->detail) {
if (MI->csh->doing_mem) {
MI->flat_insn.ppc.operands[MI->flat_insn.ppc.op_count].mem.disp = imm;
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].mem.disp = imm;
} else {
MI->flat_insn.ppc.operands[MI->flat_insn.ppc.op_count].type = PPC_OP_IMM;
MI->flat_insn.ppc.operands[MI->flat_insn.ppc.op_count].imm = imm;
MI->flat_insn.ppc.op_count++;
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = imm;
MI->flat_insn->detail->ppc.op_count++;
}
}
}
Expand Down
30 changes: 15 additions & 15 deletions arch/Sparc/SparcInstPrinter.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -43,12 +43,12 @@ static void set_mem_access(MCInst *MI, bool status)
MI->csh->doing_mem = status;

if (status) {
MI->flat_insn.sparc.operands[MI->flat_insn.sparc.op_count].type = SPARC_OP_MEM;
MI->flat_insn.sparc.operands[MI->flat_insn.sparc.op_count].mem.base = SPARC_REG_INVALID;
MI->flat_insn.sparc.operands[MI->flat_insn.sparc.op_count].mem.disp = 0;
MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].type = SPARC_OP_MEM;
MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.base = SPARC_REG_INVALID;
MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.disp = 0;
} else {
// done, create the next operand slot
MI->flat_insn.sparc.op_count++;
MI->flat_insn->detail->sparc.op_count++;
}
}

Expand Down Expand Up @@ -148,14 +148,14 @@ static void printOperand(MCInst *MI, int opNum, SStream *O)

if (MI->csh->detail) {
if (MI->csh->doing_mem) {
if (MI->flat_insn.sparc.operands[MI->flat_insn.sparc.op_count].mem.base)
MI->flat_insn.sparc.operands[MI->flat_insn.sparc.op_count].mem.index = reg;
if (MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.base)
MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.index = reg;
else
MI->flat_insn.sparc.operands[MI->flat_insn.sparc.op_count].mem.base = reg;
MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.base = reg;
} else {
MI->flat_insn.sparc.operands[MI->flat_insn.sparc.op_count].type = SPARC_OP_REG;
MI->flat_insn.sparc.operands[MI->flat_insn.sparc.op_count].reg = reg;
MI->flat_insn.sparc.op_count++;
MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].type = SPARC_OP_REG;
MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].reg = reg;
MI->flat_insn->detail->sparc.op_count++;
}
}

Expand All @@ -178,11 +178,11 @@ static void printOperand(MCInst *MI, int opNum, SStream *O)

if (MI->csh->detail) {
if (MI->csh->doing_mem) {
MI->flat_insn.sparc.operands[MI->flat_insn.sparc.op_count].mem.disp = Imm;
MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.disp = Imm;
} else {
MI->flat_insn.sparc.operands[MI->flat_insn.sparc.op_count].type = SPARC_OP_IMM;
MI->flat_insn.sparc.operands[MI->flat_insn.sparc.op_count].imm = Imm;
MI->flat_insn.sparc.op_count++;
MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].type = SPARC_OP_IMM;
MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].imm = Imm;
MI->flat_insn->detail->sparc.op_count++;
}
}
}
Expand Down Expand Up @@ -248,7 +248,7 @@ static void printCCOperand(MCInst *MI, int opNum, SStream *O)
SStream_concat(O, "%s", SPARCCondCodeToString((sparc_cc)CC));

if (MI->csh->detail)
MI->flat_insn.sparc.cc = (sparc_cc)CC;
MI->flat_insn->detail->sparc.cc = (sparc_cc)CC;
}


Expand Down
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