do not initialize some local vars unnecessarily. this problem was int…

…roduced when we fixed C89 issues for MSVC

SStream.c

@@ -18,7 +18,8 @@ void SStream_concat(SStream *ss, const char *fmt, ...)
 {
 #ifndef CAPSTONE_DIET
 	va_list ap;
-	int ret = 0;
+	int ret;
+
 	va_start(ap, fmt);
 	ret = cs_vsnprintf(ss->buffer + ss->index, sizeof(ss->buffer) - (ss->index + 1), fmt, ap);
 	va_end(ap);

arch/AArch64/AArch64BaseInfo.c

@@ -11,8 +11,8 @@
 //
 //===----------------------------------------------------------------------===//
 
-/* Capstone Disassembler Engine */
-/* By Nguyen Anh Quynh <[email protected]>, 2013> */
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <[email protected]>, 2013-2014 */
 
 #if defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64)
 #pragma warning(disable:4996)
@@ -79,7 +79,7 @@ static char *utostr(uint64_t X, bool isNeg)
 {
 	char Buffer[22];
 	char *BufPtr = Buffer+21;
-	char *result = NULL;
+	char *result;
 
 	Buffer[21] = '\0';
 	if (X == 0) *--BufPtr = '0';  // Handle special case...
@@ -577,9 +577,9 @@ static NamedImmMapper_Mapping SysRegPairs[] = {
 // result must be a big enough buffer: 128 bytes is more than enough
 void SysRegMapper_toString(SysRegMapper *S, uint32_t Bits, bool *Valid, char *result)
 {
-	int dummy = 0;
-	uint32_t Op0 = 0, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0;
-	char *Op1S = NULL, *CRnS = NULL, *CRmS = NULL, *Op2S = NULL;
+	int dummy;
+	uint32_t Op0, Op1, CRn, CRm, Op2;
+	char *Op1S, *CRnS, *CRmS, *Op2S;
 	unsigned i;
 
 	for (i = 0; i < ARR_SIZE(SysRegPairs); ++i) {
@@ -946,9 +946,9 @@ bool A64Imms_isLogicalImmBits(unsigned RegWidth, uint32_t Bits, uint64_t *Imm)
 	uint32_t N = Bits >> 12;
 	uint32_t ImmR = (Bits >> 6) & 0x3f;
 	uint32_t ImmS = Bits & 0x3f;
-	uint64_t Mask = 0, WidthMask = 0;
-	unsigned i = 0;
-	int Width = 0, Num1s = 0, Rotation = 0;
+	uint64_t Mask, WidthMask;
+	unsigned i;
+	int Width = 0, Num1s, Rotation;
 
 	// N=1 encodes a 64-bit replication and is invalid for the 32-bit
 	// instructions.
@@ -974,7 +974,8 @@ bool A64Imms_isLogicalImmBits(unsigned RegWidth, uint32_t Bits, uint64_t *Imm)
 	Num1s = (ImmS & (Width - 1)) + 1;
 
 	// All encodings which would map to -1 (signed) are RESERVED.
-	if (Num1s == Width) return false;
+	if (Num1s == Width)
+		return false;
 
 	Rotation = (ImmR & (Width - 1));
 	Mask = (1ULL << Num1s) - 1;

arch/AArch64/AArch64BaseInfo.h

@@ -14,8 +14,8 @@
 //
 //===----------------------------------------------------------------------===//
 
-/* Capstone Disassembler Engine */
-/* By Nguyen Anh Quynh <[email protected]>, 2013> */
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <[email protected]>, 2013-2014 */
 
 #ifndef CS_LLVM_AARCH64_BASEINFO_H
 #define CS_LLVM_AARCH64_BASEINFO_H

arch/AArch64/AArch64Disassembler.c

@@ -260,7 +260,7 @@ static DecodeStatus _getInstruction(cs_struct *ud, MCInst *MI,
 		uint16_t *Size,
 		uint64_t Address, MCRegisterInfo *MRI)
 {
-	uint32_t insn = 0;
+	uint32_t insn;
 	DecodeStatus result;
 
 	if (code_len < 4) {
@@ -1166,7 +1166,7 @@ static DecodeStatus DecodeVLDSTLanePostInstruction(MCInst *Inst, unsigned Insn,
 	// TransferBytes = NumVecs * OneLaneBytes
 	unsigned TransferBytes = 0;
 	unsigned NumVecs = 0;
-	unsigned Rt = 0, Rn = 0, Rm = 0, Q = 0, S = 0, lane = 0, NumLanes = 0;
+	unsigned Rt, Rn, Rm, Q, S, lane, NumLanes;
 	unsigned Opc = MCInst_getOpcode(Inst);
 	switch (Opc) {
 		case AArch64_LD1R_WB_8B_fixed: case AArch64_LD1R_WB_8B_register:

arch/AArch64/AArch64GenAsmWriter.inc

@@ -7,7 +7,7 @@
 \*===----------------------------------------------------------------------===*/
 
 /* Capstone Disassembly Engine, http://www.capstone-engine.org */
-/* By Nguyen Anh Quynh <[email protected]>, 2013> */
+/* By Nguyen Anh Quynh <[email protected]>, 2013-2014 */
 
 /// printInstruction - This method is automatically generated by tablegen
 /// from the instruction set description.
@@ -8871,7 +8871,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info)
 {
   #define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg)))
   const char *AsmString;
-  char *tmp = NULL, *AsmMnem = NULL, *AsmOps = NULL, *c = NULL;
+  char *tmp, *AsmMnem, *AsmOps, *c;
   MCRegisterInfo *MRI = (MCRegisterInfo *)info;
   switch (MCInst_getOpcode(MI)) {
   default: return NULL;

arch/AArch64/AArch64GenDisassemblerTables.inc

@@ -7,7 +7,7 @@
 \*===----------------------------------------------------------------------===*/
 
 /* Capstone Disassembly Engine, http://www.capstone-engine.org */
-/* By Nguyen Anh Quynh <[email protected]>, 2013> */
+/* By Nguyen Anh Quynh <[email protected]>, 2013-2014 */
 
 #include "../../MCInst.h"
 #include "../../LEB128.h"
@@ -14036,9 +14036,9 @@ static DecodeStatus fname(uint8_t DecodeTable[], MCInst *MI, \
 { \
   uint64_t Bits = getFeatureBits(feature); \
   uint8_t *Ptr = DecodeTable; \
-  uint32_t CurFieldValue = 0, ExpectedValue = 0; \
+  uint32_t CurFieldValue = 0, ExpectedValue; \
   DecodeStatus S = MCDisassembler_Success; \
-  unsigned Start = 0, Len = 0, NumToSkip = 0, PIdx = 0, Opc = 0, DecodeIdx = 0; \
+  unsigned Start, Len, NumToSkip, PIdx, Opc, DecodeIdx; \
   InsnType Val, FieldValue, PositiveMask, NegativeMask; \
   bool Pred, Fail; \
   for (;;) { \

arch/AArch64/AArch64InstPrinter.c

@@ -11,8 +11,8 @@
 //
 //===----------------------------------------------------------------------===//
 
-/* Capstone Disassembler Engine */
-/* By Nguyen Anh Quynh <[email protected]>, 2013> */
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <[email protected]>, 2013-2014 */
 
 #include <inttypes.h>
 #include <stdio.h>
@@ -399,7 +399,8 @@ static void printShiftOperand(MCInst *MI,  unsigned OpNum,
 		SStream *O, A64SE_ShiftExtSpecifiers Shift)
 {
 	MCOperand *MO = MCInst_getOperand(MI, OpNum);
-	unsigned int imm = 0;
+	unsigned int imm;
+
 	// LSL #0 is not printed
 	if (Shift == A64SE_LSL && MCOperand_isImm(MO) && MCOperand_getImm(MO) == 0)
 		return;
@@ -660,7 +661,7 @@ static void printNeonMovImmShiftOperand(MCInst *MI, unsigned OpNum,
 		SStream *O, A64SE_ShiftExtSpecifiers Ext, bool isHalf)
 {
 	MCOperand *MO = MCInst_getOperand(MI, OpNum);
-	int64_t Imm = 0;
+	int64_t Imm;
 	//assert(MO.isImm() &&
 	//       "Immediate operand required for Neon vector immediate inst.");
 

arch/ARM/ARMAddressingModes.h

@@ -11,8 +11,8 @@
 //
 //===----------------------------------------------------------------------===//
 
-/* Capstone Disassembler Engine */
-/* By Nguyen Anh Quynh <[email protected]>, 2013> */
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <[email protected]>, 2013-2014 */
 
 #ifndef CS_LLVM_TARGET_ARM_ARMADDRESSINGMODES_H
 #define CS_LLVM_TARGET_ARM_ARMADDRESSINGMODES_H
@@ -148,7 +148,7 @@ static inline unsigned getSOImmValRot(unsigned Imm)
 /// take a maximal chunk of bits out of the immediate.
 static inline unsigned getSOImmValRotate(unsigned Imm)
 {
-	unsigned TZ = 0, RotAmt = 0;
+	unsigned TZ, RotAmt;
 	// 8-bit (or less) immediates are trivially shifter_operands with a rotate
 	// of zero.
 	if ((Imm & ~255U) == 0) return 0;
@@ -184,7 +184,7 @@ static inline unsigned getSOImmValRotate(unsigned Imm)
 /// it.  If not, return -1.
 static inline int getSOImmVal(unsigned Arg)
 {
-	unsigned RotAmt = 0;
+	unsigned RotAmt;
 	// 8-bit (or less) immediates are trivially shifter_operands with a rotate
 	// of zero.
 	if ((Arg & ~255U) == 0) return Arg;
@@ -339,7 +339,7 @@ static inline int getT2SOImmValRotateVal(unsigned V)
 /// See ARM Reference Manual A6.3.2.
 static inline int getT2SOImmVal(unsigned Arg)
 {
-	int Rot = 0;
+	int Rot;
 	// If 'Arg' is an 8-bit splat, then get the encoded value.
 	int Splat = getT2SOImmValSplatVal(Arg);
 	if (Splat != -1)
@@ -355,8 +355,11 @@ static inline int getT2SOImmVal(unsigned Arg)
 
 static inline unsigned getT2SOImmValRotate(unsigned V)
 {
-	unsigned RotAmt = 0;
-	if ((V & ~255U) == 0) return 0;
+	unsigned RotAmt;
+
+	if ((V & ~255U) == 0)
+		return 0;
+
 	// Use CTZ to compute the rotate amount.
 	RotAmt = CountTrailingZeros_32(V);
 	return (32 - RotAmt) & 31;