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x86: properly handle SSE/AVX instructions
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@aquynh
aquynh committed Jul 15, 2016
1 parent 21b4a73 commit dabc9f2
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Showing 11 changed files with 4,587 additions and 3,750 deletions.
2 changes: 2 additions & 0 deletions .gitignore
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@@ -1,3 +1,5 @@
.DS_Store

# Object files
*.o
*.ko
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1 change: 1 addition & 0 deletions MCInst.c
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Expand Up @@ -22,6 +22,7 @@ void MCInst_Init(MCInst *inst)
inst->op1_size = 0;
inst->writeback = false;
inst->ac_idx = 0;
inst->popcode_adjust = 0;
}

void MCInst_clear(MCInst *inst)
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1 change: 1 addition & 0 deletions MCInst.h
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Expand Up @@ -107,6 +107,7 @@ struct MCInst {
bool writeback; // writeback for ARM
// operand access index for list of registers sharing the same access right (for ARM)
uint8_t ac_idx;
uint8_t popcode_adjust; // Pseudo X86 instruction adjust
};

void MCInst_Init(MCInst *inst);
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8 changes: 6 additions & 2 deletions arch/X86/X86ATTInstPrinter.c
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Expand Up @@ -225,7 +225,7 @@ static void printf512mem(MCInst *MI, unsigned OpNo, SStream *O)

static void printSSECC(MCInst *MI, unsigned Op, SStream *OS)
{
int64_t Imm = MCOperand_getImm(MCInst_getOperand(MI, Op)) & 7;
uint8_t Imm = (uint8_t)(MCOperand_getImm(MCInst_getOperand(MI, Op)) & 7);
switch (Imm) {
default: break; // never reach
case 0: SStream_concat0(OS, "eq"); op_addSseCC(MI, X86_SSE_CC_EQ); break;
Expand All @@ -237,11 +237,13 @@ static void printSSECC(MCInst *MI, unsigned Op, SStream *OS)
case 6: SStream_concat0(OS, "nle"); op_addSseCC(MI, X86_SSE_CC_NLE); break;
case 7: SStream_concat0(OS, "ord"); op_addSseCC(MI, X86_SSE_CC_ORD); break;
}

MI->popcode_adjust = Imm + 1;
}

static void printAVXCC(MCInst *MI, unsigned Op, SStream *O)
{
int64_t Imm = MCOperand_getImm(MCInst_getOperand(MI, Op)) & 0x1f;
uint8_t Imm = (uint8_t)(MCOperand_getImm(MCInst_getOperand(MI, Op)) & 0x1f);
switch (Imm) {
default: break;//printf("Invalid avxcc argument!\n"); break;
case 0: SStream_concat0(O, "eq"); op_addAvxCC(MI, X86_AVX_CC_EQ); break;
Expand Down Expand Up @@ -277,6 +279,8 @@ static void printAVXCC(MCInst *MI, unsigned Op, SStream *O)
case 0x1e: SStream_concat0(O, "gt_oq"); op_addAvxCC(MI, X86_AVX_CC_GT_OQ); break;
case 0x1f: SStream_concat0(O, "true_us"); op_addAvxCC(MI, X86_AVX_CC_TRUE_US); break;
}

MI->popcode_adjust = Imm + 1;
}

static void printXOPCC(MCInst *MI, unsigned Op, SStream *O)
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8 changes: 6 additions & 2 deletions arch/X86/X86IntelInstPrinter.c
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Expand Up @@ -256,7 +256,7 @@ static void printf512mem(MCInst *MI, unsigned OpNo, SStream *O)

static void printSSECC(MCInst *MI, unsigned Op, SStream *OS)
{
int64_t Imm = MCOperand_getImm(MCInst_getOperand(MI, Op)) & 7;
uint8_t Imm = (uint8_t)(MCOperand_getImm(MCInst_getOperand(MI, Op)) & 7);
switch (Imm) {
default: break; // never reach
case 0: SStream_concat0(OS, "eq"); op_addSseCC(MI, X86_SSE_CC_EQ); break;
Expand All @@ -268,11 +268,13 @@ static void printSSECC(MCInst *MI, unsigned Op, SStream *OS)
case 6: SStream_concat0(OS, "nle"); op_addSseCC(MI, X86_SSE_CC_NLE); break;
case 7: SStream_concat0(OS, "ord"); op_addSseCC(MI, X86_SSE_CC_ORD); break;
}

MI->popcode_adjust = Imm + 1;
}

static void printAVXCC(MCInst *MI, unsigned Op, SStream *O)
{
int64_t Imm = MCOperand_getImm(MCInst_getOperand(MI, Op)) & 0x1f;
uint8_t Imm = (uint8_t)(MCOperand_getImm(MCInst_getOperand(MI, Op)) & 0x1f);
switch (Imm) {
default: break;//printf("Invalid avxcc argument!\n"); break;
case 0: SStream_concat0(O, "eq"); op_addAvxCC(MI, X86_AVX_CC_EQ); break;
Expand Down Expand Up @@ -308,6 +310,8 @@ static void printAVXCC(MCInst *MI, unsigned Op, SStream *O)
case 0x1e: SStream_concat0(O, "gt_oq"); op_addAvxCC(MI, X86_AVX_CC_GT_OQ); break;
case 0x1f: SStream_concat0(O, "true_us"); op_addAvxCC(MI, X86_AVX_CC_TRUE_US); break;
}

MI->popcode_adjust = Imm + 1;
}

static void printXOPCC(MCInst *MI, unsigned Op, SStream *O)
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185 changes: 177 additions & 8 deletions arch/X86/X86Mapping.c
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Expand Up @@ -935,12 +935,8 @@ static name_map insn_name_maps[] = {
{ X86_INS_FCMOVU, "fcmovu" },
{ X86_INS_CMOVS, "cmovs" },
{ X86_INS_CMP, "cmp" },
{ X86_INS_CMPPD, "cmppd" },
{ X86_INS_CMPPS, "cmpps" },
{ X86_INS_CMPSB, "cmpsb" },
{ X86_INS_CMPSD, "cmpsd" },
{ X86_INS_CMPSQ, "cmpsq" },
{ X86_INS_CMPSS, "cmpss" },
{ X86_INS_CMPSW, "cmpsw" },
{ X86_INS_CMPXCHG16B, "cmpxchg16b" },
{ X86_INS_CMPXCHG, "cmpxchg" },
Expand Down Expand Up @@ -1587,10 +1583,6 @@ static name_map insn_name_maps[] = {
{ X86_INS_VBROADCASTI64X4, "vbroadcasti64x4" },
{ X86_INS_VBROADCASTSD, "vbroadcastsd" },
{ X86_INS_VBROADCASTSS, "vbroadcastss" },
{ X86_INS_VCMPPD, "vcmppd" },
{ X86_INS_VCMPPS, "vcmpps" },
{ X86_INS_VCMPSD, "vcmpsd" },
{ X86_INS_VCMPSS, "vcmpss" },
{ X86_INS_VCOMPRESSPD, "vcompresspd" },
{ X86_INS_VCOMPRESSPS, "vcompressps" },
{ X86_INS_VCVTDQ2PD, "vcvtdq2pd" },
Expand Down Expand Up @@ -2177,6 +2169,183 @@ static name_map insn_name_maps[] = {
{ X86_INS_XTEST, "xtest" },
{ X86_INS_FDISI8087_NOP, "fdisi8087_nop" },
{ X86_INS_FENI8087_NOP, "feni8087_nop" },

// pseudo instructions
{ X86_INS_CMPSS, "cmpss" },
{ X86_INS_CMPEQSS, "cmpeqss" },
{ X86_INS_CMPLTSS, "cmpltss" },
{ X86_INS_CMPLESS, "cmpless" },
{ X86_INS_CMPUNORDSS, "cmpunordss" },
{ X86_INS_CMPNEQSS, "cmpneqss" },
{ X86_INS_CMPNLTSS, "cmpnltss" },
{ X86_INS_CMPNLESS, "cmpnless" },
{ X86_INS_CMPORDSS, "cmpordss" },

{ X86_INS_CMPSD, "cmpsd" },
{ X86_INS_CMPEQSD, "cmpeqsd" },
{ X86_INS_CMPLTSD, "cmpltsd" },
{ X86_INS_CMPLESD, "cmplesd" },
{ X86_INS_CMPUNORDSD, "cmpunordsd" },
{ X86_INS_CMPNEQSD, "cmpneqsd" },
{ X86_INS_CMPNLTSD, "cmpnltsd" },
{ X86_INS_CMPNLESD, "cmpnlesd" },
{ X86_INS_CMPORDSD, "cmpordsd" },

{ X86_INS_CMPPS, "cmpps" },
{ X86_INS_CMPEQPS, "cmpeqps" },
{ X86_INS_CMPLTPS, "cmpltps" },
{ X86_INS_CMPLEPS, "cmpleps" },
{ X86_INS_CMPUNORDPS, "cmpunordps" },
{ X86_INS_CMPNEQPS, "cmpneqps" },
{ X86_INS_CMPNLTPS, "cmpnltps" },
{ X86_INS_CMPNLEPS, "cmpnleps" },
{ X86_INS_CMPORDPS, "cmpordps" },

{ X86_INS_CMPPD, "cmppd" },
{ X86_INS_CMPEQPD, "cmpeqpd" },
{ X86_INS_CMPLTPD, "cmpltpd" },
{ X86_INS_CMPLEPD, "cmplepd" },
{ X86_INS_CMPUNORDPD, "cmpunordpd" },
{ X86_INS_CMPNEQPD, "cmpneqpd" },
{ X86_INS_CMPNLTPD, "cmpnltpd" },
{ X86_INS_CMPNLEPD, "cmpnlepd" },
{ X86_INS_CMPORDPD, "cmpordpd" },

{ X86_INS_VCMPSS, "vcmpss" },
{ X86_INS_VCMPEQSS, "vcmpeqss" },
{ X86_INS_VCMPLTSS, "vcmpltss" },
{ X86_INS_VCMPLESS, "vcmpless" },
{ X86_INS_VCMPUNORDSS, "vcmpunordss" },
{ X86_INS_VCMPNEQSS, "vcmpneqss" },
{ X86_INS_VCMPNLTSS, "vcmpnltss" },
{ X86_INS_VCMPNLESS, "vcmpnless" },
{ X86_INS_VCMPORDSS, "vcmpordss" },
{ X86_INS_VCMPEQ_UQSS, "vcmpeq_uqss" },
{ X86_INS_VCMPNGESS, "vcmpngess" },
{ X86_INS_VCMPNGTSS, "vcmpngtss" },
{ X86_INS_VCMPFALSESS, "vcmpfalsess" },
{ X86_INS_VCMPNEQ_OQSS, "vcmpneq_oqss" },
{ X86_INS_VCMPGESS, "vcmpgess" },
{ X86_INS_VCMPGTSS, "vcmpgtss" },
{ X86_INS_VCMPTRUESS, "vcmptruess" },
{ X86_INS_VCMPEQ_OSSS, "vcmpeq_osss" },
{ X86_INS_VCMPLT_OQSS, "vcmplt_oqss" },
{ X86_INS_VCMPLE_OQSS, "vcmple_oqss" },
{ X86_INS_VCMPUNORD_SSS, "vcmpunord_sss" },
{ X86_INS_VCMPNEQ_USSS, "vcmpneq_usss" },
{ X86_INS_VCMPNLT_UQSS, "vcmpnlt_uqss" },
{ X86_INS_VCMPNLE_UQSS, "vcmpnle_uqss" },
{ X86_INS_VCMPORD_SSS, "vcmpord_sss" },
{ X86_INS_VCMPEQ_USSS, "vcmpeq_usss" },
{ X86_INS_VCMPNGE_UQSS, "vcmpnge_uqss" },
{ X86_INS_VCMPNGT_UQSS, "vcmpngt_uqss" },
{ X86_INS_VCMPFALSE_OSSS, "vcmpfalse_osss" },
{ X86_INS_VCMPNEQ_OSSS, "vcmpneq_osss" },
{ X86_INS_VCMPGE_OQSS, "vcmpge_oqss" },
{ X86_INS_VCMPGT_OQSS, "vcmpgt_oqss" },
{ X86_INS_VCMPTRUE_USSS, "vcmptrue_usss" },

{ X86_INS_VCMPSD, "vcmpsd" },
{ X86_INS_VCMPEQSD, "vcmpeqsd" },
{ X86_INS_VCMPLTSD, "vcmpltsd" },
{ X86_INS_VCMPLESD, "vcmplesd" },
{ X86_INS_VCMPUNORDSD, "vcmpunordsd" },
{ X86_INS_VCMPNEQSD, "vcmpneqsd" },
{ X86_INS_VCMPNLTSD, "vcmpnltsd" },
{ X86_INS_VCMPNLESD, "vcmpnlesd" },
{ X86_INS_VCMPORDSD, "vcmpordsd" },
{ X86_INS_VCMPEQ_UQSD, "vcmpeq_uqsd" },
{ X86_INS_VCMPNGESD, "vcmpngesd" },
{ X86_INS_VCMPNGTSD, "vcmpngtsd" },
{ X86_INS_VCMPFALSESD, "vcmpfalsesd" },
{ X86_INS_VCMPNEQ_OQSD, "vcmpneq_oqsd" },
{ X86_INS_VCMPGESD, "vcmpgesd" },
{ X86_INS_VCMPGTSD, "vcmpgtsd" },
{ X86_INS_VCMPTRUESD, "vcmptruesd" },
{ X86_INS_VCMPEQ_OSSD, "vcmpeq_ossd" },
{ X86_INS_VCMPLT_OQSD, "vcmplt_oqsd" },
{ X86_INS_VCMPLE_OQSD, "vcmple_oqsd" },
{ X86_INS_VCMPUNORD_SSD, "vcmpunord_ssd" },
{ X86_INS_VCMPNEQ_USSD, "vcmpneq_ussd" },
{ X86_INS_VCMPNLT_UQSD, "vcmpnlt_uqsd" },
{ X86_INS_VCMPNLE_UQSD, "vcmpnle_uqsd" },
{ X86_INS_VCMPORD_SSD, "vcmpord_ssd" },
{ X86_INS_VCMPEQ_USSD, "vcmpeq_ussd" },
{ X86_INS_VCMPNGE_UQSD, "vcmpnge_uqsd" },
{ X86_INS_VCMPNGT_UQSD, "vcmpngt_uqsd" },
{ X86_INS_VCMPFALSE_OSSD, "vcmpfalse_ossd" },
{ X86_INS_VCMPNEQ_OSSD, "vcmpneq_ossd" },
{ X86_INS_VCMPGE_OQSD, "vcmpge_oqsd" },
{ X86_INS_VCMPGT_OQSD, "vcmpgt_oqsd" },
{ X86_INS_VCMPTRUE_USSD, "vcmptrue_ussd" },

{ X86_INS_VCMPPS, "vcmpps" },
{ X86_INS_VCMPEQPS, "vcmpeqps" },
{ X86_INS_VCMPLTPS, "vcmpltps" },
{ X86_INS_VCMPLEPS, "vcmpleps" },
{ X86_INS_VCMPUNORDPS, "vcmpunordps" },
{ X86_INS_VCMPNEQPS, "vcmpneqps" },
{ X86_INS_VCMPNLTPS, "vcmpnltps" },
{ X86_INS_VCMPNLEPS, "vcmpnleps" },
{ X86_INS_VCMPORDPS, "vcmpordps" },
{ X86_INS_VCMPEQ_UQPS, "vcmpeq_uqps" },
{ X86_INS_VCMPNGEPS, "vcmpngeps" },
{ X86_INS_VCMPNGTPS, "vcmpngtps" },
{ X86_INS_VCMPFALSEPS, "vcmpfalseps" },
{ X86_INS_VCMPNEQ_OQPS, "vcmpneq_oqps" },
{ X86_INS_VCMPGEPS, "vcmpgeps" },
{ X86_INS_VCMPGTPS, "vcmpgtps" },
{ X86_INS_VCMPTRUEPS, "vcmptrueps" },
{ X86_INS_VCMPEQ_OSPS, "vcmpeq_osps" },
{ X86_INS_VCMPLT_OQPS, "vcmplt_oqps" },
{ X86_INS_VCMPLE_OQPS, "vcmple_oqps" },
{ X86_INS_VCMPUNORD_SPS, "vcmpunord_sps" },
{ X86_INS_VCMPNEQ_USPS, "vcmpneq_usps" },
{ X86_INS_VCMPNLT_UQPS, "vcmpnlt_uqps" },
{ X86_INS_VCMPNLE_UQPS, "vcmpnle_uqps" },
{ X86_INS_VCMPORD_SPS, "vcmpord_sps" },
{ X86_INS_VCMPEQ_USPS, "vcmpeq_usps" },
{ X86_INS_VCMPNGE_UQPS, "vcmpnge_uqps" },
{ X86_INS_VCMPNGT_UQPS, "vcmpngt_uqps" },
{ X86_INS_VCMPFALSE_OSPS, "vcmpfalse_osps" },
{ X86_INS_VCMPNEQ_OSPS, "vcmpneq_osps" },
{ X86_INS_VCMPGE_OQPS, "vcmpge_oqps" },
{ X86_INS_VCMPGT_OQPS, "vcmpgt_oqps" },
{ X86_INS_VCMPTRUE_USPS, "vcmptrue_usps" },

{ X86_INS_VCMPPD, "vcmppd" },
{ X86_INS_VCMPEQPD, "vcmpeqpd" },
{ X86_INS_VCMPLTPD, "vcmpltpd" },
{ X86_INS_VCMPLEPD, "vcmplepd" },
{ X86_INS_VCMPUNORDPD, "vcmpunordpd" },
{ X86_INS_VCMPNEQPD, "vcmpneqpd" },
{ X86_INS_VCMPNLTPD, "vcmpnltpd" },
{ X86_INS_VCMPNLEPD, "vcmpnlepd" },
{ X86_INS_VCMPORDPD, "vcmpordpd" },
{ X86_INS_VCMPEQ_UQPD, "vcmpeq_uqpd" },
{ X86_INS_VCMPNGEPD, "vcmpngepd" },
{ X86_INS_VCMPNGTPD, "vcmpngtpd" },
{ X86_INS_VCMPFALSEPD, "vcmpfalsepd" },
{ X86_INS_VCMPNEQ_OQPD, "vcmpneq_oqpd" },
{ X86_INS_VCMPGEPD, "vcmpgepd" },
{ X86_INS_VCMPGTPD, "vcmpgtpd" },
{ X86_INS_VCMPTRUEPD, "vcmptruepd" },
{ X86_INS_VCMPEQ_OSPD, "vcmpeq_ospd" },
{ X86_INS_VCMPLT_OQPD, "vcmplt_oqpd" },
{ X86_INS_VCMPLE_OQPD, "vcmple_oqpd" },
{ X86_INS_VCMPUNORD_SPD, "vcmpunord_spd" },
{ X86_INS_VCMPNEQ_USPD, "vcmpneq_uspd" },
{ X86_INS_VCMPNLT_UQPD, "vcmpnlt_uqpd" },
{ X86_INS_VCMPNLE_UQPD, "vcmpnle_uqpd" },
{ X86_INS_VCMPORD_SPD, "vcmpord_spd" },
{ X86_INS_VCMPEQ_USPD, "vcmpeq_uspd" },
{ X86_INS_VCMPNGE_UQPD, "vcmpnge_uqpd" },
{ X86_INS_VCMPNGT_UQPD, "vcmpngt_uqpd" },
{ X86_INS_VCMPFALSE_OSPD, "vcmpfalse_ospd" },
{ X86_INS_VCMPNEQ_OSPD, "vcmpneq_ospd" },
{ X86_INS_VCMPGE_OQPD, "vcmpge_oqpd" },
{ X86_INS_VCMPGT_OQPD, "vcmpgt_oqpd" },
{ X86_INS_VCMPTRUE_USPD, "vcmptrue_uspd" },
};
#endif

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