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Commits on Mar 4, 2015

• 2015

  aquynh

  committed
  bfcaba5

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Commits on Sep 1, 2014

• arm: update core with a lot more details provided in detail mode now. update Python & Java bindings to reflect the core's changes

  aquynh

  committed
  04d9f8e

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Commits on May 27, 2014

• Disassembler -> Disassembly

  aquynh

  committed
  f721e31

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Commits on May 19, 2014

• x86: add immediate operand (1) for SHL/SHR/ROR/ROL/SAR/SAL in detail mode & Intel syntax

  aquynh

  committed
  6456481

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Commits on Mar 10, 2014

• arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')

  aquynh

  committed
  2ff665a

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Commits on Dec 14, 2013

• detail option: provide instruction id even when detail option is OFF

  aquynh

  committed
  4d3e852

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Commits on Dec 12, 2013

• x86: handle outs instruction in 16bit mode

  aquynh

  committed
  a01d154

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Commits on Dec 11, 2013

• Use const on all read-only buffers

  radare

  committed
  f0e4eed

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Commits on Nov 27, 2013

• initial import

  aquynh

  committed
  26ee41a

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