ITE: drivers/i2c: adjust timing registers to pass SI test

Timing registers of I2C 0/1/2 can be adjusted to pass SI test. We can control the tSU;STA and tHD;DAT simultaneously by changing the value of the register IT83XX_SMB_4P7USL, and we can control the tSU;DAT by changing the value of the register IT83XX_SMB_250NS as well. Signed-off-by: Tim Lin <[email protected]>
hooloong · Mar 17, 2022 · 14bac3f · 14bac3f
1 parent f2c4266
commit 14bac3f
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/drivers/i2c/i2c_ite_it8xxx2.c b/drivers/i2c/i2c_ite_it8xxx2.c
@@ -187,10 +187,10 @@ static void i2c_standard_port_timing_regs_400khz(uint8_t port)
 	/* Port clock frequency depends on setting of timing registers. */
 	IT8XXX2_SMB_SCLKTS(port) = 0;
 	/* Suggested setting of timing registers of 400kHz. */
-	IT8XXX2_SMB_4P7USL = 0x6;
+	IT8XXX2_SMB_4P7USL = 0x3;
 	IT8XXX2_SMB_4P0USL = 0;
 	IT8XXX2_SMB_300NS = 0x1;
-	IT8XXX2_SMB_250NS = 0x2;
+	IT8XXX2_SMB_250NS = 0x5;
 	IT8XXX2_SMB_45P3USL = 0x6a;
 	IT8XXX2_SMB_45P3USH = 0x1;
 	IT8XXX2_SMB_4P7A4P0H = 0;