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Merge branch 'confprec'
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Conflicts:
	Makefile
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qmn committed Jan 20, 2014
2 parents d372a0e + 612076a commit 714662a
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2 changes: 1 addition & 1 deletion Makefile
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Expand Up @@ -4,7 +4,7 @@ ENV_H := ../riscv-tests/env/encoding.h
GAS_H := ../riscv-gcc/binutils-2.21.1/include/opcode/riscv-opc.h
XCC_H := ../riscv-gcc/gcc-4.6.1/gcc/config/riscv/riscv-opc.h

ALL_OPCODES := opcodes opcodes-pseudo opcodes-rvc opcodes-hwacha opcodes-hwacha-pseudo opcodes-custom
ALL_OPCODES := opcodes opcodes-pseudo opcodes-rvc opcodes-hwacha opcodes-hwacha-pseudo opcodes-hwacha-ut opcodes-custom

install: $(ISASIM_H) $(PK_H) $(ENV_H) $(GAS_H) $(XCC_H) inst.chisel instr-table.tex

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1 change: 1 addition & 0 deletions opcodes-hwacha
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Expand Up @@ -11,6 +11,7 @@ fmovn 31..25=3 rs2 rs1 14..12=7 rd 6..2=0x1D 1..0=3
# vector instructions
vsetcfg imm12 rs1 14=0 13=1 12=0 11..7=0 6..2=0x02 1..0=3
vsetvl 31..25=0 24..20=0 rs1 14=1 13=1 12=0 rd 6..2=0x02 1..0=3
vsetprec imm12 19..15=1 14=0 13=0 12=0 11..7=0 6..2=0x16 1..0=3
vgetcfg 31..25=0 24..20=0 19..15=0 14=1 13=0 12=0 rd 6..2=0x02 1..0=3
vgetvl 31..25=1 24..20=0 19..15=0 14=1 13=0 12=0 rd 6..2=0x02 1..0=3

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55 changes: 55 additions & 0 deletions opcodes-hwacha-ut
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# format of a line in this file:
# <instruction name> <args> <opcode>
#
# <opcode> is given by specifying one or more range/value pairs:
# hi..lo=value or bit=value or arg=value (e.g. 6..2=0x45 10=1 rd=0)
#
# <args> is one of rd, rs1, rs2, rs3, imm25, imm20, imm12, imm12lo, imm12hi,
# shamtw, shamt, rm

# half-precision floating-point operations for hwacha microthreads

fadd.h rd rs1 rs2 31..27=0x0 rm 26..25=2 6..2=0x14 1..0=3
fsub.h rd rs1 rs2 31..27=0x1 rm 26..25=2 6..2=0x14 1..0=3
fmul.h rd rs1 rs2 31..27=0x2 rm 26..25=2 6..2=0x14 1..0=3
fdiv.h rd rs1 rs2 31..27=0x3 rm 26..25=2 6..2=0x14 1..0=3
fsqrt.h rd rs1 24..20=0 31..27=0x4 rm 26..25=2 6..2=0x14 1..0=3
fsgnj.h rd rs1 rs2 31..27=0x5 14..12=0 26..25=2 6..2=0x14 1..0=3
fsgnjn.h rd rs1 rs2 31..27=0x6 14..12=0 26..25=2 6..2=0x14 1..0=3
fsgnjx.h rd rs1 rs2 31..27=0x7 14..12=0 26..25=2 6..2=0x14 1..0=3

fcvt.h.l rd rs1 24..20=0 31..27=0xC rm 26..25=2 6..2=0x14 1..0=3
fcvt.h.lu rd rs1 24..20=0 31..27=0xD rm 26..25=2 6..2=0x14 1..0=3
fcvt.h.w rd rs1 24..20=0 31..27=0xE rm 26..25=2 6..2=0x14 1..0=3
fcvt.h.wu rd rs1 24..20=0 31..27=0xF rm 26..25=2 6..2=0x14 1..0=3

fcvt.l.h rd rs1 24..20=0 31..27=0x8 rm 26..25=2 6..2=0x14 1..0=3
fcvt.lu.h rd rs1 24..20=0 31..27=0x9 rm 26..25=2 6..2=0x14 1..0=3
fcvt.w.h rd rs1 24..20=0 31..27=0xA rm 26..25=2 6..2=0x14 1..0=3
fcvt.wu.h rd rs1 24..20=0 31..27=0xB rm 26..25=2 6..2=0x14 1..0=3

fcvt.s.h rd rs1 24..20=0 31..29=0x4 28..27=0 rm 26..25=2 6..2=0x14 1..0=3
fcvt.h.s rd rs1 24..20=0 31..29=0x4 28..27=2 rm 26..25=0 6..2=0x14 1..0=3

fcvt.d.h rd rs1 24..20=0 31..29=0x4 28..27=1 rm 26..25=2 6..2=0x14 1..0=3
fcvt.h.d rd rs1 24..20=0 31..29=0x4 28..27=2 rm 26..25=1 6..2=0x14 1..0=3

feq.h rd rs1 rs2 31..27=0x15 14..12=0 26..25=2 6..2=0x14 1..0=3
flt.h rd rs1 rs2 31..27=0x16 14..12=0 26..25=2 6..2=0x14 1..0=3
fle.h rd rs1 rs2 31..27=0x17 14..12=0 26..25=2 6..2=0x14 1..0=3

fmin.h rd rs1 rs2 31..27=0x18 14..12=0 26..25=2 6..2=0x14 1..0=3
fmax.h rd rs1 rs2 31..27=0x19 14..12=0 26..25=2 6..2=0x14 1..0=3

fmv.x.h rd rs1 24..20=0 31..27=0x1C 14..12=0 26..25=2 6..2=0x14 1..0=3
fmv.h.x rd rs1 24..20=0 31..27=0x1E 14..12=0 26..25=2 6..2=0x14 1..0=3

flh rd rs1 imm12 14..12=1 6..2=0x01 1..0=3

fsh imm12hi rs1 rs2 imm12lo 14..12=1 6..2=0x09 1..0=3

fmadd.h rd rs1 rs2 rs3 rm 26..25=2 6..2=0x10 1..0=3
fmsub.h rd rs1 rs2 rs3 rm 26..25=2 6..2=0x11 1..0=3
fnmsub.h rd rs1 rs2 rs3 rm 26..25=2 6..2=0x12 1..0=3
fnmadd.h rd rs1 rs2 rs3 rm 26..25=2 6..2=0x13 1..0=3

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