armv8: LS2080A: Consolidate LS2080A and LS2085A

LS2080A is the primary SoC, and LS2085A is a personality with AIOP and DPAA DDR. The RDB and QDS boards support both personality. By detecting the SVR at runtime, a single image per board can support both SoCs. It gives users flexibility to swtich SoC without the need to reprogram the board. Signed-off-by: York Sun <[email protected]> CC: Prabhakar Kushwaha <[email protected]> Reviewed-by: Prabhakar Kushwaha <[email protected]>
hou-X · Apr 6, 2016 · 3c1d218 · 3c1d218
1 parent 2a55583
commit 3c1d218
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Showing 36 changed files with 115 additions and 248 deletions.
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
@@ -25,10 +25,6 @@ ifneq ($(CONFIG_LS2080A),)
 obj-$(CONFIG_SYS_HAS_SERDES) += ls2080a_serdes.o
 endif
 
-ifneq ($(CONFIG_LS2085A),)
-obj-$(CONFIG_SYS_HAS_SERDES) += ls2080a_serdes.o
-endif
-
 ifneq ($(CONFIG_LS1043A),)
 obj-$(CONFIG_SYS_HAS_SERDES) += ls1043a_serdes.o
 endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -538,12 +538,12 @@ int print_cpuinfo(void)
 	struct sys_info sysinfo;
 	char buf[32];
 	unsigned int i, core;
-	u32 type, rcw;
+	u32 type, rcw, svr = gur_in32(&gur->svr);
 
 	puts("SoC: ");
 
 	cpu_name(buf);
-	printf(" %s (0x%x)\n", buf, gur_in32(&gur->svr));
+	printf(" %s (0x%x)\n", buf, svr);
 	memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
 	get_sys_info(&sysinfo);
 	puts("Clock Configuration:");
@@ -564,7 +564,10 @@ int print_cpuinfo(void)
 	printf("  FMAN:     %-4s MHz", strmhz(buf, sysinfo.freq_fman[0]));
 #endif
 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
-	printf("     DP-DDR:   %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus2));
+	if (soc_has_dp_ddr()) {
+		printf("     DP-DDR:   %-4s MT/s",
+		       strmhz(buf, sysinfo.freq_ddrbus2));
+	}
 #endif
 	puts("\n");
 

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
@@ -97,9 +97,13 @@ void get_sys_info(struct sys_info *sys_info)
 			FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) &
 			FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK;
 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
-	sys_info->freq_ddrbus2 *= (gur_in32(&gur->rcwsr[0]) >>
+	if (soc_has_dp_ddr()) {
+		sys_info->freq_ddrbus2 *= (gur_in32(&gur->rcwsr[0]) >>
 			FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT) &
 			FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK;
+	} else {
+		sys_info->freq_ddrbus2 = 0;
+	}
 #endif
 
 	for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
@@ -20,7 +20,7 @@ ENTRY(lowlevel_init)
 #ifdef CONFIG_FSL_LSCH3
 
 	/* Set Wuo bit for RN-I 20 */
-#if defined(CONFIG_LS2085A) || defined (CONFIG_LS2080A)
+#ifdef CONFIG_LS2080A
 	ldr	x0, =CCI_AUX_CONTROL_BASE(20)
 	ldr	x1, =0x00000010
 	bl	ccn504_set_aux

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -18,7 +18,31 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+bool soc_has_dp_ddr(void)
+{
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	u32 svr = gur_in32(&gur->svr);
+
+	/* LS2085A has DP_DDR */
+	if (SVR_SOC_VER(svr) == SVR_LS2085)
+		return true;
+
+	return false;
+}
+
+bool soc_has_aiop(void)
+{
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	u32 svr = gur_in32(&gur->svr);
+
+	/* LS2085A has AIOP */
+	if (SVR_SOC_VER(svr) == SVR_LS2085)
+		return true;
+
+	return false;
+}
+
+#ifdef CONFIG_LS2080A
 /*
  * This erratum requires setting a value to eddrtqcr1 to
  * optimal the DDR performance.

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c
@@ -46,15 +46,15 @@ void board_init_f(ulong dummy)
 {
 	/* Clear global data */
 	memset((void *)gd, 0, sizeof(gd_t));
-#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+#ifdef CONFIG_LS2080A
 	arch_cpu_init();
 #endif
 #ifdef CONFIG_FSL_IFC
 	init_early_memctl_regs();
 #endif
 	board_early_init_f();
 	timer_init();
-#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+#ifdef CONFIG_LS2080A
 	env_init();
 #endif
 	get_clocks();

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -23,16 +23,11 @@
  */
 #define CONFIG_SYS_MEM_RESERVE_SECURE	(2048 * 1024)	/* 2MB */
 
-#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+#ifdef CONFIG_LS2080A
 #define CONFIG_MAX_CPUS				16
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT		8
-#ifdef CONFIG_LS2080A
-#define CONFIG_NUM_DDR_CONTROLLERS		2
-#endif
-#ifdef CONFIG_LS2085A
 #define CONFIG_NUM_DDR_CONTROLLERS		3
-#define CONFIG_SYS_FSL_HAS_DP_DDR
-#endif
+#define CONFIG_SYS_FSL_HAS_DP_DDR		/* Runtime check to confirm */
 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS		{ 1, 1, 4, 4 }
 #define	SRDS_MAX_LANES	8
 #define CONFIG_SYS_FSL_SRDS_1

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
@@ -206,7 +206,7 @@ static const struct sys_mmu_table final_mmu_table[] = {
 	{ CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
 	  CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE,
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
-#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+#ifdef CONFIG_LS2080A
 	{ CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
 	  CONFIG_SYS_PCIE4_PHYS_SIZE, MT_DEVICE_NGNRNE,
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
@@ -9,7 +9,7 @@
 
 #include <config.h>
 
-#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+#ifdef CONFIG_LS2080A
 enum srds_prtcl {
 	NONE = 0,
 	PCIE1,

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -94,4 +94,7 @@ void cpu_name(char *name);
 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
 void erratum_a009635(void);
 #endif
+
+bool soc_has_dp_ddr(void);
+bool soc_has_aiop(void);
 #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */
diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h
@@ -44,15 +44,14 @@
 
 #endif
 
-#if defined(CONFIG_LS1043A) || defined(CONFIG_LS2080A) ||\
-	defined(CONFIG_LS2085A)
+#if defined(CONFIG_LS1043A) || defined(CONFIG_LS2080A)
 /* For LS1043 (ARMv8), ESBC image Address in Header is 64 bit
- * Similiarly for LS2080 and LS2085
+ * Similiarly for LS2080
  */
 #define CONFIG_ESBC_ADDR_64BIT
 #endif
 
-#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+#ifdef CONFIG_LS2080A
 #define CONFIG_EXTRA_ENV \
 	"setenv fdt_high 0xa0000000;"	\
 	"setenv initrd_high 0xcfffffff;"	\
@@ -66,12 +65,11 @@
 
 /* Copying Bootscript and Header to DDR from NOR for LS2 and for rest, from
  * Non-XIP Memory (Nand/SD)*/
-#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_LS2080A) ||\
-	defined(CONFIG_LS2085A)
+#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_LS2080A)
 #define CONFIG_BOOTSCRIPT_COPY_RAM
 #endif
 /* The address needs to be modified according to NOR and DDR memory map */
-#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+#ifdef CONFIG_LS2080A
 #define CONFIG_BS_HDR_ADDR_FLASH	0x583920000
 #define CONFIG_BS_ADDR_FLASH		0x583900000
 #define CONFIG_BS_HDR_ADDR_RAM		0xa3920000

diff --git a/board/freescale/ls2080a/MAINTAINERS b/board/freescale/ls2080a/MAINTAINERS
@@ -6,5 +6,3 @@ F:	include/configs/ls2080a_emu.h
 F:	configs/ls2080a_emu_defconfig
 F:	include/configs/ls2080a_simu.h
 F:	configs/ls2080a_simu_defconfig
-F:	configs/ls2085a_emu_defconfig
-F:	configs/ls2085a_simu_defconfig
diff --git a/board/freescale/ls2080a/ddr.c b/board/freescale/ls2080a/ddr.c
@@ -7,6 +7,7 @@
 #include <common.h>
 #include <fsl_ddr_sdram.h>
 #include <fsl_ddr_dimm_params.h>
+#include <asm/arch/soc.h>
 #include "ddr.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -201,22 +202,24 @@ void dram_init_banksize(void)
 	}
 
 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
-	/* initialize DP-DDR here */
-	puts("DP-DDR:  ");
-	/*
-	 * DDR controller use 0 as the base address for binding.
-	 * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
-	 */
-	dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
+	if (soc_has_dp_ddr()) {
+		/* initialize DP-DDR here */
+		puts("DP-DDR:  ");
+		/*
+		 * DDR controller use 0 as the base address for binding.
+		 * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
+		 */
+		dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
 					  CONFIG_DP_DDR_CTRL,
 					  CONFIG_DP_DDR_NUM_CTRLS,
 					  CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
 					  NULL, NULL, NULL);
-	if (dp_ddr_size) {
-		gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
-		gd->bd->bi_dram[2].size = dp_ddr_size;
-	} else {
-		puts("Not detected");
+		if (dp_ddr_size) {
+			gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
+			gd->bd->bi_dram[2].size = dp_ddr_size;
+		} else {
+			puts("Not detected");
+		}
 	}
 #endif
 }
diff --git a/board/freescale/ls2080a/ls2080a.c b/board/freescale/ls2080a/ls2080a.c
@@ -42,7 +42,7 @@ void detail_board_ddr_info(void)
 	print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
 	print_ddr_info(0);
 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
-	if (gd->bd->bi_dram[2].size) {
+	if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
 		puts("\nDP-DDR ");
 		print_size(gd->bd->bi_dram[2].size, "");
 		print_ddr_info(CONFIG_DP_DDR_CTRL);

diff --git a/board/freescale/ls2080aqds/MAINTAINERS b/board/freescale/ls2080aqds/MAINTAINERS
@@ -6,11 +6,8 @@ F:	board/freescale/ls2080a/ls2080aqds.c
 F:	include/configs/ls2080aqds.h
 F:	configs/ls2080aqds_defconfig
 F:	configs/ls2080aqds_nand_defconfig
-F:	configs/ls2085aqds_defconfig
-F:	configs/ls2085aqds_nand_defconfig
 
 LS2080A_SECURE_BOOT BOARD
 M:	Saksham Jain <[email protected]>
 S:	Maintained
 F:	configs/ls2080aqds_SECURE_BOOT_defconfig
-F:	configs/ls2085aqds_SECURE_BOOT_defconfig
diff --git a/board/freescale/ls2080aqds/ddr.c b/board/freescale/ls2080aqds/ddr.c
@@ -7,6 +7,7 @@
 #include <common.h>
 #include <fsl_ddr_sdram.h>
 #include <fsl_ddr_dimm_params.h>
+#include <asm/arch/soc.h>
 #include "ddr.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -201,22 +202,24 @@ void dram_init_banksize(void)
 	}
 
 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
-	/* initialize DP-DDR here */
-	puts("DP-DDR:  ");
-	/*
-	 * DDR controller use 0 as the base address for binding.
-	 * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
-	 */
-	dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
+	if (soc_has_dp_ddr()) {
+		/* initialize DP-DDR here */
+		puts("DP-DDR:  ");
+		/*
+		 * DDR controller use 0 as the base address for binding.
+		 * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
+		 */
+		dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
 					  CONFIG_DP_DDR_CTRL,
 					  CONFIG_DP_DDR_NUM_CTRLS,
 					  CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
 					  NULL, NULL, NULL);
-	if (dp_ddr_size) {
-		gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
-		gd->bd->bi_dram[2].size = dp_ddr_size;
-	} else {
-		puts("Not detected");
+		if (dp_ddr_size) {
+			gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
+			gd->bd->bi_dram[2].size = dp_ddr_size;
+		} else {
+			puts("Not detected");
+		}
 	}
 #endif
 }
diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c
@@ -228,7 +228,7 @@ void detail_board_ddr_info(void)
 	print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
 	print_ddr_info(0);
 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
-	if (gd->bd->bi_dram[2].size) {
+	if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
 		puts("\nDP-DDR ");
 		print_size(gd->bd->bi_dram[2].size, "");
 		print_ddr_info(CONFIG_DP_DDR_CTRL);

diff --git a/board/freescale/ls2080ardb/MAINTAINERS b/board/freescale/ls2080ardb/MAINTAINERS
@@ -6,11 +6,8 @@ F:	board/freescale/ls2080a/ls2080ardb.c
 F:	include/configs/ls2080ardb.h
 F:	configs/ls2080ardb_defconfig
 F:	configs/ls2080ardb_nand_defconfig
-F:	configs/ls2085ardb_defconfig
-F:	configs/ls2085ardb_nand_defconfig
 
 LS2080A_SECURE_BOOT BOARD
 M:	Saksham Jain <[email protected]>
 S:	Maintained
 F:	configs/ls2080ardb_SECURE_BOOT_defconfig
-F:	configs/ls2085ardb_SECURE_BOOT_defconfig
diff --git a/board/freescale/ls2080ardb/ddr.c b/board/freescale/ls2080ardb/ddr.c
@@ -7,6 +7,7 @@
 #include <common.h>
 #include <fsl_ddr_sdram.h>
 #include <fsl_ddr_dimm_params.h>
+#include <asm/arch/soc.h>
 #include "ddr.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -201,22 +202,24 @@ void dram_init_banksize(void)
 	}
 
 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
-	/* initialize DP-DDR here */
-	puts("DP-DDR:  ");
-	/*
-	 * DDR controller use 0 as the base address for binding.
-	 * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
-	 */
-	dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
+	if (soc_has_dp_ddr()) {
+		/* initialize DP-DDR here */
+		puts("DP-DDR:  ");
+		/*
+		 * DDR controller use 0 as the base address for binding.
+		 * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
+		 */
+		dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
 					  CONFIG_DP_DDR_CTRL,
 					  CONFIG_DP_DDR_NUM_CTRLS,
 					  CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
 					  NULL, NULL, NULL);
-	if (dp_ddr_size) {
-		gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
-		gd->bd->bi_dram[2].size = dp_ddr_size;
-	} else {
-		puts("Not detected");
+		if (dp_ddr_size) {
+			gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
+			gd->bd->bi_dram[2].size = dp_ddr_size;
+		} else {
+			puts("Not detected");
+		}
 	}
 #endif
 }
diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c
@@ -207,7 +207,7 @@ void detail_board_ddr_info(void)
 	print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
 	print_ddr_info(0);
 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
-	if (gd->bd->bi_dram[2].size) {
+	if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
 		puts("\nDP-DDR ");
 		print_size(gd->bd->bi_dram[2].size, "");
 		print_ddr_info(CONFIG_DP_DDR_CTRL);