net: phy: dp83867: Convert 6 wire mode to ti,sgmii-ref-clock-output-e…

…nable

Changes have been done in mainline Linux by commit a2111c460c0c
("net: phy: dp83867: Add documentation for SGMII mode type")
and by commit 507ddd5c0d47 ("net: phy: dp83867: Add SGMII mode type switching")

It means align dt property, macro names and variable names to match
mainline Linux.

Signed-off-by: Michal Simek <[email protected]>

doc/device-tree-bindings/net/ti,dp83867.txt

@@ -12,11 +12,16 @@ Required properties:
 		compensate for the board being designed with the lanes swapped.
 	- enet-phy-no-lane-swap - Indicates that PHY will disable swap of the
 		TX/RX lanes.
+
+Optional property:
 	- ti,clk-output-sel - Muxing option for CLK_OUT pin.  See dt-bindings/net/ti-dp83867.h
 			      for applicable values.  The CLK_OUT pin can also
 			      be disabled by this property.  When omitted, the
 			      PHY's default will be left as is.
-	- ti,6-wire-mode - Indicates that it enables SGMII differntial clock to MAC
+	- ti,sgmii-ref-clock-output-enable - This denotes which
+				    SGMII configuration is used (4 or 6-wire modes).
+				    Some MACs work with differential SGMII clock.
+				    See data manual for details.
 
 Default child nodes are standard Ethernet PHY device
 nodes as described in doc/devicetree/bindings/net/ethernet.txt

drivers/net/phy/dp83867.c

@@ -28,7 +28,7 @@
 #define DP83867_STRAP_STS2	0x006f
 #define DP83867_RGMIIDCTL	0x0086
 #define DP83867_IO_MUX_CFG	0x0170
-#define DP83867_SGMIITYPE	0x00D3
+#define DP83867_SGMIICTL	0x00D3
 
 #define DP83867_SW_RESET	BIT(15)
 #define DP83867_SW_RESTART	BIT(14)
@@ -101,7 +101,8 @@
 /* CFG4 bits */
 #define DP83867_CFG4_PORT_MIRROR_EN		BIT(0)
 
-#define DP83867_SGMIICLK_EN			0x4000
+/* SGMIICTL bits */
+#define DP83867_SGMII_TYPE			BIT(14)
 
 enum {
 	DP83867_PORT_MIRRORING_KEEP,
@@ -118,7 +119,7 @@ struct dp83867_private {
 	int port_mirroring;
 	bool set_clk_output;
 	unsigned int clk_output_sel;
-	bool wiremode_6;
+	bool sgmii_ref_clk_en;
 };
 
 static int dp83867_config_port_mirroring(struct phy_device *phydev)
@@ -239,11 +240,8 @@ static int dp83867_of_init(struct phy_device *phydev)
 	if (ofnode_read_bool(node, "enet-phy-lane-no-swap"))
 		dp83867->port_mirroring = DP83867_PORT_MIRRORING_DIS;
 
-	/*
-	 * 6-wire mode enables differential SGMII clock to MAC
-	 */
-	if (ofnode_read_bool(node, "ti,6-wire-mode"))
-		dp83867->wiremode_6 = true;
+	if (ofnode_read_bool(node, "ti,sgmii-ref-clock-output-enable"))
+		dp83867->sgmii_ref_clk_en = true;
 
 	return 0;
 }
@@ -338,9 +336,9 @@ static int dp83867_config(struct phy_device *phydev)
 		phy_write_mmd(phydev, DP83867_DEVADDR,
 			      DP83867_RGMIIDCTL, delay);
 	} else if (phy_interface_is_sgmii(phydev)) {
-		if (dp83867->wiremode_6)
-			phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIITYPE,
-				      DP83867_SGMIICLK_EN);
+		if (dp83867->sgmii_ref_clk_en)
+			phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL,
+				      DP83867_SGMII_TYPE);
 
 		phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR,
 			  (BMCR_ANENABLE | BMCR_FULLDPLX | BMCR_SPEED1000));