chore: remove repetitive words (capstone-engine#2326)

Signed-off-by: careworry <[email protected]> chore: remove repetitive words
hwhohwh · Apr 22, 2024 · 16017d5 · 16017d5
1 parent 7746648
commit 16017d5
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Showing 10 changed files with 10 additions and 10 deletions.
diff --git a/arch/AArch64/AArch64Mapping.c b/arch/AArch64/AArch64Mapping.c
@@ -926,7 +926,7 @@ static void add_cs_detail_general(MCInst *MI, aarch64_op_group op_group,
 			break;
 		case AArch64_OP_FP: {
 			// printOperand does not handle FP operands. But sometimes
-			// is is used to print FP operands as normal immediate.
+			// is used to print FP operands as normal immediate.
 			AArch64_get_detail_op(MI, 0)->type = AArch64_OP_IMM;
 			AArch64_get_detail_op(MI, 0)->imm = MCInst_getOpVal(MI, OpNum);
 			AArch64_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum);

diff --git a/arch/M680X/M680XDisassembler.c b/arch/M680X/M680XDisassembler.c
@@ -209,7 +209,7 @@ static bool read_sdword(const m680x_info *info, int32_t *sdword,
 	return true;
 }
 
-// For PAGE2 and PAGE3 opcodes when using an an array of inst_page1 most
+// For PAGE2 and PAGE3 opcodes when using an array of inst_page1 most
 // entries have M680X_INS_ILLGL. To avoid wasting memory an inst_pageX is
 // used which contains the opcode. Using a binary search for the right opcode
 // is much faster (= O(log n) ) in comparison to a linear search ( = O(n) ).

diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h b/suite/synctools/tablegen/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
@@ -781,7 +781,7 @@ class MachineIRBuilder {
   ///
   /// \pre setBasicBlock or setMI must have been called.
   /// \pre \p TablePtr must be a generic virtual register with pointer type.
-  /// \pre \p JTI must be be a jump table index.
+  /// \pre \p JTI must be a jump table index.
   /// \pre \p IndexReg must be a generic virtual register with pointer type.
   ///
   /// \return a MachineInstrBuilder for the newly created instruction.

diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/ISDOpcodes.h b/suite/synctools/tablegen/include/llvm/CodeGen/ISDOpcodes.h
@@ -865,7 +865,7 @@ enum NodeType {
   STRICT_FP_TO_FP16,
 
   /// Perform various unary floating-point operations inspired by libm. For
-  /// FPOWI, the result is undefined if if the integer operand doesn't fit into
+  /// FPOWI, the result is undefined if the integer operand doesn't fit into
   /// sizeof(int).
   FNEG,
   FABS,

diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/ScheduleDAG.h b/suite/synctools/tablegen/include/llvm/CodeGen/ScheduleDAG.h
@@ -758,7 +758,7 @@ class TargetRegisterInfo;
     /// be added from SUnit \p X to SUnit \p Y.
     void AddPredQueued(SUnit *Y, SUnit *X);
 
-    /// Updates the topological ordering to accommodate an an edge to be
+    /// Updates the topological ordering to accommodate an edge to be
     /// removed from the specified node \p N from the predecessors of the
     /// current node \p M.
     void RemovePred(SUnit *M, SUnit *N);

diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/TargetLowering.h b/suite/synctools/tablegen/include/llvm/CodeGen/TargetLowering.h
@@ -3187,7 +3187,7 @@ class TargetLoweringBase {
   ///      is[Z|FP]ExtFree of the related types is not true.
   virtual bool isExtFreeImpl(const Instruction *I) const { return false; }
 
-  /// Depth that GatherAllAliases should should continue looking for chain
+  /// Depth that GatherAllAliases should continue looking for chain
   /// dependencies when trying to find a more preferable chain. As an
   /// approximation, this should be more than the number of consecutive stores
   /// expected to be merged.

diff --git a/suite/synctools/tablegen/include/llvm/IR/InstrTypes.h b/suite/synctools/tablegen/include/llvm/IR/InstrTypes.h
@@ -1699,7 +1699,7 @@ class CallBase : public Instruction {
            paramHasAttr(ArgNo, Attribute::DereferenceableOrNull);
   }
 
-  /// Determine if there are is an inalloca argument. Only the last argument can
+  /// Determine if there is an inalloca argument. Only the last argument can
   /// have the inalloca attribute.
   bool hasInAllocaArgument() const {
     return !arg_empty() && paramHasAttr(arg_size() - 1, Attribute::InAlloca);

diff --git a/suite/synctools/tablegen/include/llvm/IR/LegacyPassManagers.h b/suite/synctools/tablegen/include/llvm/IR/LegacyPassManagers.h
@@ -424,7 +424,7 @@ class PMDataManager {
   SmallVector<Pass *, 16> PassVector;
 
   // Collection of Analysis provided by Parent pass manager and
-  // used by current pass manager. At at time there can not be more
+  // used by current pass manager. At time there can not be more
   // then PMT_Last active pass mangers.
   DenseMap<AnalysisID, Pass *> *InheritedAnalysis[PMT_Last];
 

diff --git a/suite/synctools/tablegen/include/llvm/IR/PassManagerInternal.h b/suite/synctools/tablegen/include/llvm/IR/PassManagerInternal.h
@@ -52,7 +52,7 @@ struct PassConcept {
   /// Polymorphic method to access the name of a pass.
   virtual StringRef name() const = 0;
 
-  /// Polymorphic method to to let a pass optionally exempted from skipping by
+  /// Polymorphic method to let a pass optionally exempted from skipping by
   /// PassInstrumentation.
   /// To opt-in, pass should implement `static bool isRequired()`. It's no-op
   /// to have `isRequired` always return false since that is the default.

diff --git a/suite/synctools/tablegen/include/llvm/Target/Target.td b/suite/synctools/tablegen/include/llvm/Target/Target.td
@@ -301,7 +301,7 @@ class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
   string DiagnosticType = "";
 
   // A diagnostic message to emit when an invalid value is provided for this
-  // register class when it is being used an an assembly operand. If this is
+  // register class when it is being used an assembly operand. If this is
   // non-empty, an anonymous diagnostic type enum value will be generated, and
   // the assembly matcher will provide a function to map from diagnostic types
   // to message strings.