Fixed an assert by the ARM disassembler for LDRD_PRE/POST.

The relevant instruction table entries were changed sometime ago to no longer take
<Rt2> as an operand.  Modify ARMDisassemblerCore.cpp to accomodate the change and
add a test case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127935 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp

@@ -1163,8 +1163,9 @@ static bool DisassembleLdStMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
                                                      decodeRd(insn))));
   ++OpIdx;
 
-  // Fill in LDRD and STRD's second operand.
-  if (DualReg) {
+  // Fill in LDRD and STRD's second operand, but only if it's offset mode OR we
+  // have a pre-or-post-indexed store operation.
+  if (DualReg && (!isPrePost || isStore)) {
     MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
                                                        decodeRd(insn) + 1)));
     ++OpIdx;
@@ -1186,7 +1187,7 @@ static bool DisassembleLdStMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
   assert(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
          "Reg operand expected");
   assert((!isPrePost || (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1))
-         && "Index mode or tied_to operand expected");
+         && "Offset mode or tied_to operand expected");
   MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
                                                      decodeRn(insn))));
   ++OpIdx;

test/MC/Disassembler/ARM/arm-tests.txt

@@ -160,3 +160,6 @@
 
 # CHECK:	strdeq	r2, r3, [r0], -r8
 0xf8 0x24 0x00 0x00
+
+# CHECK:	ldrdeq	r2, [r0], -r12
+0xdc 0x24 0x00 0x00