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R600/SI: remove image sample writemask
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Signed-off-by: Christian König <[email protected]>
Reviewed-by: Michel Dänzer <[email protected]>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179164 91177308-0d34-0410-b5e6-96231b3b80d8
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@ChristianKoenigAMD
ChristianKoenigAMD committed Apr 10, 2013
1 parent 4e31728 commit 9c210da
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Showing 3 changed files with 30 additions and 31 deletions.
25 changes: 12 additions & 13 deletions lib/Target/R600/SIInstructions.td
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Original file line number Diff line number Diff line change
Expand Up @@ -1219,49 +1219,48 @@ def : Pat <

/* int_SI_sample for simple 1D texture lookup */
def : Pat <
(int_SI_sample imm:$writemask, VReg_32:$addr,
SReg_256:$rsrc, SReg_128:$sampler, imm),
(IMAGE_SAMPLE imm:$writemask, 0, 0, 0, 0, 0, 0, 0, VReg_32:$addr,
(int_SI_sample VReg_32:$addr, SReg_256:$rsrc, SReg_128:$sampler, imm),
(IMAGE_SAMPLE 0xf, 0, 0, 0, 0, 0, 0, 0, VReg_32:$addr,
SReg_256:$rsrc, SReg_128:$sampler)
>;

class SamplePattern<Intrinsic name, MIMG opcode, RegisterClass addr_class,
ValueType addr_type> : Pat <
(name imm:$writemask, (addr_type addr_class:$addr),
(name (addr_type addr_class:$addr),
SReg_256:$rsrc, SReg_128:$sampler, imm),
(opcode imm:$writemask, 0, 0, 0, 0, 0, 0, 0, addr_class:$addr,
(opcode 0xf, 0, 0, 0, 0, 0, 0, 0, addr_class:$addr,
SReg_256:$rsrc, SReg_128:$sampler)
>;

class SampleRectPattern<Intrinsic name, MIMG opcode, RegisterClass addr_class,
ValueType addr_type> : Pat <
(name imm:$writemask, (addr_type addr_class:$addr),
(name (addr_type addr_class:$addr),
SReg_256:$rsrc, SReg_128:$sampler, TEX_RECT),
(opcode imm:$writemask, 1, 0, 0, 0, 0, 0, 0, addr_class:$addr,
(opcode 0xf, 1, 0, 0, 0, 0, 0, 0, addr_class:$addr,
SReg_256:$rsrc, SReg_128:$sampler)
>;

class SampleArrayPattern<Intrinsic name, MIMG opcode, RegisterClass addr_class,
ValueType addr_type> : Pat <
(name imm:$writemask, (addr_type addr_class:$addr),
(name (addr_type addr_class:$addr),
SReg_256:$rsrc, SReg_128:$sampler, TEX_ARRAY),
(opcode imm:$writemask, 0, 0, 1, 0, 0, 0, 0, addr_class:$addr,
(opcode 0xf, 0, 0, 1, 0, 0, 0, 0, addr_class:$addr,
SReg_256:$rsrc, SReg_128:$sampler)
>;

class SampleShadowPattern<Intrinsic name, MIMG opcode,
RegisterClass addr_class, ValueType addr_type> : Pat <
(name imm:$writemask, (addr_type addr_class:$addr),
(name (addr_type addr_class:$addr),
SReg_256:$rsrc, SReg_128:$sampler, TEX_SHADOW),
(opcode imm:$writemask, 0, 0, 0, 0, 0, 0, 0, addr_class:$addr,
(opcode 0xf, 0, 0, 0, 0, 0, 0, 0, addr_class:$addr,
SReg_256:$rsrc, SReg_128:$sampler)
>;

class SampleShadowArrayPattern<Intrinsic name, MIMG opcode,
RegisterClass addr_class, ValueType addr_type> : Pat <
(name imm:$writemask, (addr_type addr_class:$addr),
(name (addr_type addr_class:$addr),
SReg_256:$rsrc, SReg_128:$sampler, TEX_SHADOW_ARRAY),
(opcode imm:$writemask, 0, 0, 1, 0, 0, 0, 0, addr_class:$addr,
(opcode 0xf, 0, 0, 1, 0, 0, 0, 0, addr_class:$addr,
SReg_256:$rsrc, SReg_128:$sampler)
>;

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2 changes: 1 addition & 1 deletion lib/Target/R600/SIIntrinsics.td
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Original file line number Diff line number Diff line change
Expand Up @@ -19,7 +19,7 @@ let TargetPrefix = "SI", isTarget = 1 in {
def int_SI_load_const : Intrinsic <[llvm_float_ty], [llvm_v16i8_ty, llvm_i32_ty], [IntrNoMem]>;
def int_SI_vs_load_input : Intrinsic <[llvm_v4f32_ty], [llvm_v16i8_ty, llvm_i16_ty, llvm_i32_ty], [IntrNoMem]> ;

class Sample : Intrinsic <[llvm_v4f32_ty], [llvm_i32_ty, llvm_anyvector_ty, llvm_v32i8_ty, llvm_v16i8_ty, llvm_i32_ty], [IntrNoMem]>;
class Sample : Intrinsic <[llvm_v4f32_ty], [llvm_anyvector_ty, llvm_v32i8_ty, llvm_v16i8_ty, llvm_i32_ty], [IntrNoMem]>;

def int_SI_sample : Sample;
def int_SI_sampleb : Sample;
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34 changes: 17 additions & 17 deletions test/CodeGen/R600/llvm.SI.sample.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -34,37 +34,37 @@ define void @test(i32 %a1, i32 %a2, i32 %a3, i32 %a4) {
%v14 = insertelement <4 x i32> undef, i32 %a4, i32 1
%v15 = insertelement <4 x i32> undef, i32 %a4, i32 2
%v16 = insertelement <4 x i32> undef, i32 %a4, i32 3
%res1 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v1,
%res1 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v1,
<8 x i32> undef, <4 x i32> undef, i32 1)
%res2 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v2,
%res2 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v2,
<8 x i32> undef, <4 x i32> undef, i32 2)
%res3 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v3,
%res3 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v3,
<8 x i32> undef, <4 x i32> undef, i32 3)
%res4 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v4,
%res4 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v4,
<8 x i32> undef, <4 x i32> undef, i32 4)
%res5 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v5,
%res5 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v5,
<8 x i32> undef, <4 x i32> undef, i32 5)
%res6 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v6,
%res6 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v6,
<8 x i32> undef, <4 x i32> undef, i32 6)
%res7 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v7,
%res7 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v7,
<8 x i32> undef, <4 x i32> undef, i32 7)
%res8 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v8,
%res8 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v8,
<8 x i32> undef, <4 x i32> undef, i32 8)
%res9 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v9,
%res9 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v9,
<8 x i32> undef, <4 x i32> undef, i32 9)
%res10 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v10,
%res10 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v10,
<8 x i32> undef, <4 x i32> undef, i32 10)
%res11 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v11,
%res11 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v11,
<8 x i32> undef, <4 x i32> undef, i32 11)
%res12 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v12,
%res12 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v12,
<8 x i32> undef, <4 x i32> undef, i32 12)
%res13 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v13,
%res13 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v13,
<8 x i32> undef, <4 x i32> undef, i32 13)
%res14 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v14,
%res14 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v14,
<8 x i32> undef, <4 x i32> undef, i32 14)
%res15 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v15,
%res15 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v15,
<8 x i32> undef, <4 x i32> undef, i32 15)
%res16 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v16,
%res16 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v16,
<8 x i32> undef, <4 x i32> undef, i32 16)
%e1 = extractelement <4 x float> %res1, i32 0
%e2 = extractelement <4 x float> %res2, i32 0
Expand Down Expand Up @@ -101,6 +101,6 @@ define void @test(i32 %a1, i32 %a2, i32 %a3, i32 %a4) {
ret void
}

declare <4 x float> @llvm.SI.sample.(i32, <4 x i32>, <8 x i32>, <4 x i32>, i32) readnone
declare <4 x float> @llvm.SI.sample.(<4 x i32>, <8 x i32>, <4 x i32>, i32) readnone

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

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