This method belonged in VirtRegMap.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126002 91177308-0d34-0410-b5e6-96231b3b80d8
hylsd · Feb 19, 2011 · fd38917 · fd38917
1 parent a2ebf60
commit fd38917
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Showing 3 changed files with 10 additions and 10 deletions.
diff --git a/lib/CodeGen/LiveRangeEdit.cpp b/lib/CodeGen/LiveRangeEdit.cpp
@@ -19,18 +19,13 @@
 
 using namespace llvm;
 
-unsigned LiveRangeEdit::getOriginal(const VirtRegMap &vrm) const {
-  unsigned Orig = vrm.getPreSplitReg(getReg());
-  return Orig ? Orig : getReg();
-}
-
 LiveInterval &LiveRangeEdit::create(MachineRegisterInfo &mri,
                                     LiveIntervals &lis,
                                     VirtRegMap &vrm) {
   const TargetRegisterClass *RC = mri.getRegClass(getReg());
   unsigned VReg = mri.createVirtualRegister(RC);
   vrm.grow();
-  vrm.setIsSplitFromReg(VReg, getOriginal(vrm));
+  vrm.setIsSplitFromReg(VReg, vrm.getOriginal(getReg()));
   LiveInterval &li = lis.getOrCreateInterval(VReg);
   newRegs_.push_back(&li);
   return li;

diff --git a/lib/CodeGen/LiveRangeEdit.h b/lib/CodeGen/LiveRangeEdit.h
@@ -73,10 +73,6 @@ class LiveRangeEdit {
   LiveInterval &getParent() const { return parent_; }
   unsigned getReg() const { return parent_.reg; }
 
-  /// getOriginal - Return the original virtual register that parent descends
-  /// from through splitting. The original was not created by splitting.
-  unsigned getOriginal(const VirtRegMap&) const;
-
   /// Iterator for accessing the new registers added by this edit.
   typedef SmallVectorImpl<LiveInterval*>::const_iterator iterator;
   iterator begin() const { return newRegs_.begin()+firstNew_; }

diff --git a/lib/CodeGen/VirtRegMap.h b/lib/CodeGen/VirtRegMap.h
@@ -218,6 +218,15 @@ namespace llvm {
       return Virt2SplitMap[virtReg];
     }
 
+    /// getOriginal - Return the original virtual register that VirtReg descends
+    /// from through splitting.
+    /// A register that was not created by splitting is its own original.
+    /// This operation is idempotent.
+    unsigned getOriginal(unsigned VirtReg) const {
+      unsigned Orig = getPreSplitReg(VirtReg);
+      return Orig ? Orig : VirtReg;
+    }
+
     /// @brief returns true if the specified virtual register is not
     /// mapped to a stack slot or rematerialized.
     bool isAssignedReg(unsigned virtReg) const {