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Commits on Apr 26, 2013

• Re-write the address propagation code for pre-indexed loads/stores to take into account some previously misssed cases (PRE_DEC addressing mode, the offset and base address are swapped, etc). This s…

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  730a570

Commits on Apr 25, 2013

• Fix constant folding for one lane vector types. Constant folding one lane vector types not returns a vector instead of a scalar.

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  0206683

Commits on Mar 27, 2013

• Enabling the generation of dependency breakers for partial updates on Cortex-A15. Also fixing a small bug in getting the update clearence for VLD1LNd32.

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Commits on Mar 15, 2013

• Adding an A15 specific optimization pass for interactions between S/D/Q registers. The pass handles all the required transformations pre-regalloc.

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  bcbf3fd

Commits on Jan 25, 2013

• Fixed the condition codes for the atomic64 min/umin code generation on ARM. If the sutraction of the higher 32 bit parts gives a 0 result, we need to do the store operation.

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Commits on Jan 7, 2013

• Make the MergeGlobals pass correctly handle the address space qualifiers of the global variables. We partition the set of globals by their address space, and apply the same the trasnformation as be…

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Commits on Nov 29, 2012

• Added atomic 64 min/max/umin/umax instrinsics support in the ARM backend.

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  35b3df6

Commits on Oct 15, 2012

• Fixed PR13938: the ARM backend was crashing because it couldn't select a VDUPLANE node with the vector input size different from the output size. This was bacause the BUILD_VECTOR lowering code did…

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Commits on Oct 3, 2012

• Fixed a bug in the ExecutionDependencyFix pass that caused dependencies to not propagate through implicit defs.

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Commits on Sep 17, 2012

• Removed the VMLxForwarding feature for the Cortex-A15 target.

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Commits on Sep 13, 2012

• This patch introduces A15 as a target in LLVM.

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  616471d

Commits on Sep 5, 2012

• Fixed the DAG combiner to better handle the folding of AND nodes for vector types. The previous code was making the assumption that the length of the bitmask returned by isConstantSplat was equal t…

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  3d5e161

Commits on May 11, 2012

• Added the missing bit definition for the 4th bit of the STR (post reg) instruction. It is now set to 0. The patch also sets the unpredictable mask for SEL and SXTB-type instructions.

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  169e9ba

• Fixed the LLVM ARM v7 assembler and instruction printer for 8-bit immediate offset addressing. The assembler and instruction printer were not properly handeling the #-0 immediate.

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  ca3cd41

Commits on May 3, 2012

• Fixed disassembler for vstm/vldm ARM VFP instructions.

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Commits on Apr 18, 2012

• Added support for disassembling unpredictable swp/swpb ARM instructions.

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  35ee7d2

• Fix the bahavior of the disassembler when decoding unpredictable mrs instructions on ARM. Now the diasassembler emmits warnings instead of errors.

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  6b9f97d

• Added support for unpredictable mcrr/mcrr2/mrrc/mrrc2 ARM instruction in the disassembler. Since the upredicability conditions are complex, C++ code was added to handle them.

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  fa1ebc6

• Fixed decoding for the ARM cdp2 instruction. The restriction on the coprocessor number was removed for this instruction.

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  e546c4c

• Add suport for unpredicatble cases of the cmp, tst, teq and cmnz ARM instructions in the disassembler.

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  9e71231

Commits on Apr 5, 2012

• Added support for unpredictable ADC/SBC instructions on ARM, and also fixed some corner cases involving the PC register as an operand for these instructions.

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• Added support for handling unpredictable arithmetic instructions on ARM.

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Commits on Apr 2, 2012

• Second part for the 153874 one

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• Added fix in TableGen instruction decoder generation. The decoder now breaks for every leaf node.

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Commits on Mar 22, 2012

• Added soft fail checks for the disassembler when decoding some corner cases of the STRD, STRH, LDRD, LDRH, LDRSH and LDRSB instructions on ARM.

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• Added soft fail cases for the disassembler when decoding LDRSBT, LDRHT or LDRSHT instruction on ARM

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• Added soft fail cases for the disassembler when decoding MUL instructions on ARM.

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Commits on Mar 20, 2012

• The ARM instructions that have an unpredictable behavior when the pc register operand is given now fail with soft fail. Modified the regression tests to reflect this.

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• test commit

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  8da7a46