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Commits on Jul 2, 2014

• R600: Add a comment that llvm.AMDGPU.trunc is a legacy intrinsic

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• R600/SI: Use a ComplexPattern for ADDR64 addressing of MUBUF loads

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• R600: Promote i64 loads to v2i32

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• R600/SI: Adjsut SGPR live ranges before register allocation

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• R600/SI: Add verifier check for immediates in register operands.

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Commits on Jun 24, 2014

• R600/SI: Use a ComplexPattern for MUBUF stores

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• R600: Promote i64 stores to v2i32

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Commits on Jun 20, 2014

• R600/SI: Add patterns for ctpop inside a branch

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• R600/SI: Add a pattern for f32 ftrunc

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• R600: Expand vector flog2

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• R600: Expand vector fexp2

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• R600/SI: SI Control Flow Annotation bug fixed

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• R600/SI: Add a VALU pattern for i64 xor

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Commits on Jun 17, 2014

• R600/SI: Make sure target flags are set on pseudo VOP3 instructions

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• R600: Use LDS and vectors for private memory

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• R600/SI: Add a pattern for llvm.AMDGPU.barrier.global

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• SelectionDAG: Expand i64 = FP_TO_SINT i32

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• R600/SI: Re-initialize the m0 register after using it for indirect addressing

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Commits on Jun 13, 2014

• R600: Remove AMDIL instruction and register definitions

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• R600: Move AMDGPUInstrInfo from AMDGPUTargetMachine into AMDGPUSubtarget

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• R600: Drop use of cached TargetMachine in R600InstrInfo.cpp

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• R600: Drop use of cached TargetMachine in AMDGPUInstrInfo.cpp

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Commits on Jun 12, 2014

• Revert "SelectionDAG: Enable (and (setcc x), (setcc y)) -> (setcc (and x, y)) for vectors"

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Commits on Jun 11, 2014

• R600: Set correct InstrItinClass for instructions using *Helper classes

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• R600: BCNT_INT is a vector only instruction

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Commits on Jun 10, 2014

• R600/SI: Emit an error when attempting to spill VGPRs v4

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• R600/SI: Fix a crash when spilling SGPRs

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• Hexagon: Expand i1 SELECT_CC

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• SelectionDAG: Don't use MVT::Other to determine legality of ISD::SELECT_CC

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• SelectionDAG: Enable (and (setcc x), (setcc y)) -> (setcc (and x, y)) for vectors

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• SelectionDAG: Expand SELECT_CC to SELECT + SETCC

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Commits on May 16, 2014

• R600/SI: Refactor the VOP3_32 tablegen class

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• R600/SI: Add a PredicateControl class for managing TableGen predicates

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• R600/SI: Move tablegen patterns away from instruction defs

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• R600/SI: Remove unused instruction

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