MIPS: mm: c-r4k: Set the correct ISA level

The local_r4k_flush_cache_sigtramp function uses the 'cache' instruction inside an asm block. However, MIPS R6 changed the opcode for the cache instruction and as a result of which we need to set the correct ISA level. Signed-off-by: Markos Chandras <[email protected]>
iegor · Feb 17, 2015 · 4ee4862 · 4ee4862
1 parent 77f3ee5
commit 4ee4862
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
@@ -794,7 +794,7 @@ static void local_r4k_flush_cache_sigtramp(void * arg)
 		__asm__ __volatile__ (
 			".set push\n\t"
 			".set noat\n\t"
-			".set mips3\n\t"
+			".set "MIPS_ISA_LEVEL"\n\t"
 #ifdef CONFIG_32BIT
 			"la	$at,1f\n\t"
 #endif