ram: Introduce K3 AM654 DDR Sub System driver

K3 based AM654 devices has DDR memory subsystem that comprises
Synopys DDR controller, Synopsis DDR phy and wrapper logic to
intergrate these blocks into the device. This DDR subsystem
provides an interface to external SDRAM devices. Adding support
for the initialization of the external SDRAM devices by
configuring the DDRSS registers and using the buitin PHY
routines.

Reviewed-by: Tom Rini <[email protected]>
Signed-off-by: Lokesh Vutla <[email protected]>
Signed-off-by: Andreas Dannenberg <[email protected]>
Signed-off-by: Keerthy <[email protected]>
Signed-off-by: Schuyler Patton <[email protected]>
Signed-off-by: James Doublesin <[email protected]>

arch/arm/mach-k3/include/mach/sys_proto.h

@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ *	Andreas Dannenberg <[email protected]>
+ */
+
+#ifndef _SYS_PROTO_H_
+#define _SYS_PROTO_H_
+
+void sdelay(unsigned long loops);
+u32 wait_on_value(u32 read_bit_mask, u32 match_value, void *read_addr,
+		  u32 bound);
+
+#endif

doc/device-tree-bindings/ram/k3-am654-ddrss.txt

@@ -0,0 +1,46 @@
+Texas Instruments' K3 AM654 DDRSS
+=================================
+
+K3 based AM654 devices has DDR memory subsystem that comprises
+Synopys DDR controller, Synopsis DDR phy and wrapper logic to
+integrate these blocks into the device. This DDR subsystem
+provides an interface to external SDRAM devices. This DDRSS driver
+adds support for the initialization of the external SDRAM devices by
+configuring the DDRSS registers and using the buitin PHY
+initialization routines.
+
+DDRSS device node:
+==================
+Required properties:
+--------------------
+- compatible:		Shall be: "ti,am654-ddrss"
+- reg-names 		ss - Map the sub system wrapper logic region
+			ctl - Map the controller region
+			phy - Map the PHY region
+- reg:			Contains the register map per reg-names.
+- power-domains:	Should contain a phandle to a PM domain provider node
+			and an args specifier containing the DDRSS device id
+			value. This property is as per the binding,
+			doc/device-tree-bindings/power/ti,sci-pm-domain.txt
+- clocks:		Must contain an entry for enabling DDR clock. Should
+			be defined as per the appropriate clock bindings consumer
+			usage in doc/device-tree-bindings/clock/ti,sci-clk.txt
+
+
+Optional Properties:
+--------------------
+- clock-frequency:	Frequency at which DDR pll should be locked.
+			If not provided, default frequency will be used.
+
+Example (AM65x):
+================
+		memory-controller: memory-controller@298e000 {
+			compatible = "ti,am654-ddrss";
+			reg = <0x0298e000 0x200>,
+				<0x02980000 0x4000>,
+				<0x02988000 0x2000>;
+			reg-names = "ss", "ctl", "phy";
+			clocks = <&k3_clks 20 0>;
+			power-domains = <&k3_pds 20>;
+			u-boot,dm-spl;
+		};

drivers/ram/Kconfig

@@ -43,4 +43,15 @@ config MPC83XX_SDRAM
 	  the RAM through the use of SPD (Serial Presence Detect) is supported
 	  via device tree settings.
 
+config K3_AM654_DDRSS
+	bool "Enable AM654 DDRSS support"
+	depends on RAM && SOC_K3_AM6
+	help
+	  K3 based AM654 devices has DDR memory subsystem that comprises
+	  Synopys DDR controller, Synopsis DDR phy and wrapper logic to
+	  intergrate these blocks into the device. This DDR subsystem
+	  provides an interface to external SDRAM devices. Enabling this
+	  config add support for the initialization of the external
+	  SDRAM devices connected to DDR subsystem.
+
 source "drivers/ram/stm32mp1/Kconfig"

drivers/ram/Makefile

@@ -11,3 +11,5 @@ obj-$(CONFIG_STM32_SDRAM) += stm32_sdram.o
 obj-$(CONFIG_ARCH_BMIPS) += bmips_ram.o
 
 obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
+
+obj-$(CONFIG_K3_AM654_DDRSS) += k3-am654-ddrss.o