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arm: at91: wdt: Convert watchdog driver to dm/dt
Convert the Watchdog driver for AT91SAM9x processors to support the driver model and device tree. Changes "CONFIG_AT91SAM9_WATCHDOG" to new "CONFIG_WDT_AT91" Kconfig option. Signed-off-by: Prasanthi Chellakumar <[email protected]>
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@@ -89,6 +89,7 @@ | |
}; | ||
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watchdog@fffffd40 { | ||
timeout-sec = <15>; | ||
status = "okay"; | ||
}; | ||
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@@ -98,6 +98,7 @@ | |
}; | ||
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watchdog@fffffd40 { | ||
timeout-sec = <15>; | ||
status = "okay"; | ||
}; | ||
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@@ -4,7 +4,7 @@ | |
* | ||
* Copyright (C) 2008 Jean-Christophe PLAGNIOL-VILLARD <[email protected]> | ||
* Copyright (C) 2007 Andrew Victor | ||
* Copyright (C) 2007 Atmel Corporation. | ||
* Copyright (C) 2018 Microchip Technology Inc. | ||
* | ||
* Watchdog Timer (WDT) - System peripherals regsters. | ||
* Based on AT91SAM9261 datasheet revision D. | ||
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@@ -27,9 +27,13 @@ typedef struct at91_wdt { | |
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#endif | ||
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/* Watchdog Control Register */ | ||
#define AT91_WDT_CR 0x00 | ||
#define AT91_WDT_CR_WDRSTT 1 | ||
#define AT91_WDT_CR_KEY 0xa5000000 /* KEY Password */ | ||
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/* Watchdog Mode Register*/ | ||
#define AT91_WDT_MR 0X04 | ||
#define AT91_WDT_MR_WDV(x) (x & 0xfff) | ||
#define AT91_WDT_MR_WDFIEN 0x00001000 | ||
#define AT91_WDT_MR_WDRSTEN 0x00002000 | ||
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@@ -3,7 +3,7 @@ | |
# (C) Copyright 2008 | ||
# Wolfgang Denk, DENX Software Engineering, [email protected]. | ||
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obj-$(CONFIG_AT91SAM9_WATCHDOG) += at91sam9_wdt.o | ||
obj-$(CONFIG_WDT_AT91) += at91sam9_wdt.o | ||
obj-$(CONFIG_FTWDT010_WATCHDOG) += ftwdt010_wdt.o | ||
ifneq (,$(filter $(SOC), mx25 mx31 mx35 mx5 mx6 mx7 vf610)) | ||
obj-y += imx_watchdog.o | ||
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@@ -2,7 +2,7 @@ | |
/* | ||
* [origin: Linux kernel drivers/watchdog/at91sam9_wdt.c] | ||
* | ||
* Watchdog driver for Atmel AT91SAM9x processors. | ||
* Watchdog driver for AT91SAM9x processors. | ||
* | ||
* Copyright (C) 2008 Jean-Christophe PLAGNIOL-VILLARD <[email protected]> | ||
* Copyright (C) 2008 Renaud CERRATO [email protected] | ||
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@@ -14,38 +14,47 @@ | |
* write to this register. Inform Linux to it too | ||
*/ | ||
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#include <common.h> | ||
#include <watchdog.h> | ||
#include <asm/arch/hardware.h> | ||
#include <asm/io.h> | ||
#include <asm/arch/at91_wdt.h> | ||
#include <common.h> | ||
#include <dm.h> | ||
#include <errno.h> | ||
#include <wdt.h> | ||
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DECLARE_GLOBAL_DATA_PTR; | ||
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/* | ||
* AT91SAM9 watchdog runs a 12bit counter @ 256Hz, | ||
* use this to convert a watchdog | ||
* value from/to milliseconds. | ||
* value from seconds. | ||
*/ | ||
#define ms_to_ticks(t) (((t << 8) / 1000) - 1) | ||
#define ticks_to_ms(t) (((t + 1) * 1000) >> 8) | ||
#define WDT_SEC2TICKS(s) (((s) << 8) - 1) | ||
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/* Hardware timeout in seconds */ | ||
#if !defined(CONFIG_AT91_HW_WDT_TIMEOUT) | ||
#define WDT_HW_TIMEOUT 2 | ||
#else | ||
#define WDT_HW_TIMEOUT CONFIG_AT91_HW_WDT_TIMEOUT | ||
#endif | ||
#define WDT_MAX_TIMEOUT 16 | ||
#define WDT_MIN_TIMEOUT 0 | ||
#define WDT_DEFAULT_TIMEOUT 2 | ||
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struct at91_wdt_priv { | ||
void __iomem *regs; | ||
u32 regval; | ||
u32 timeout; | ||
}; | ||
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/* | ||
* Set the watchdog time interval in 1/256Hz (write-once) | ||
* Counter is 12 bit. | ||
*/ | ||
static int at91_wdt_settimeout(unsigned int timeout) | ||
static int at91_wdt_start(struct udevice *dev, u64 timeout_s, ulong flags) | ||
{ | ||
unsigned int reg; | ||
at91_wdt_t *wd = (at91_wdt_t *) ATMEL_BASE_WDT; | ||
struct at91_wdt_priv *priv = dev_get_priv(dev); | ||
u32 timeout = WDT_SEC2TICKS(timeout_s); | ||
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if (timeout_s > WDT_MAX_TIMEOUT || timeout_s < WDT_MIN_TIMEOUT) | ||
timeout = priv->timeout; | ||
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/* Check if disabled */ | ||
if (readl(&wd->mr) & AT91_WDT_MR_WDDIS) { | ||
if (readl(priv->regs + AT91_WDT_MR) & AT91_WDT_MR_WDDIS) { | ||
printf("sorry, watchdog is disabled\n"); | ||
return -1; | ||
} | ||
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@@ -57,24 +66,71 @@ static int at91_wdt_settimeout(unsigned int timeout) | |
* 4096 / 256 = 16 seconds. | ||
*/ | ||
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reg = AT91_WDT_MR_WDRSTEN /* causes watchdog reset */ | ||
priv->regval = AT91_WDT_MR_WDRSTEN /* causes watchdog reset */ | ||
| AT91_WDT_MR_WDDBGHLT /* disabled in debug mode */ | ||
| AT91_WDT_MR_WDD(0xfff) /* restart at any time */ | ||
| AT91_WDT_MR_WDV(timeout); /* timer value */ | ||
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writel(reg, &wd->mr); | ||
writel(priv->regval, priv->regs + AT91_WDT_MR); | ||
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return 0; | ||
} | ||
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static int at91_wdt_stop(struct udevice *dev) | ||
{ | ||
struct at91_wdt_priv *priv = dev_get_priv(dev); | ||
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/* Disable Watchdog Timer */ | ||
priv->regval |= AT91_WDT_MR_WDDIS; | ||
writel(priv->regval, priv->regs + AT91_WDT_MR); | ||
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return 0; | ||
} | ||
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void hw_watchdog_reset(void) | ||
static int at91_wdt_reset(struct udevice *dev) | ||
{ | ||
at91_wdt_t *wd = (at91_wdt_t *) ATMEL_BASE_WDT; | ||
writel(AT91_WDT_CR_WDRSTT | AT91_WDT_CR_KEY, &wd->cr); | ||
struct at91_wdt_priv *priv = dev_get_priv(dev); | ||
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writel(AT91_WDT_CR_WDRSTT | AT91_WDT_CR_KEY, priv->regs + AT91_WDT_CR); | ||
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return 0; | ||
} | ||
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void hw_watchdog_init(void) | ||
static const struct wdt_ops at91_wdt_ops = { | ||
.start = at91_wdt_start, | ||
.stop = at91_wdt_stop, | ||
.reset = at91_wdt_reset, | ||
}; | ||
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static const struct udevice_id at91_wdt_ids[] = { | ||
{ .compatible = "atmel,at91sam9260-wdt" }, | ||
{} | ||
}; | ||
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static int at91_wdt_probe(struct udevice *dev) | ||
{ | ||
/* 16 seconds timer, resets enabled */ | ||
at91_wdt_settimeout(ms_to_ticks(WDT_HW_TIMEOUT * 1000)); | ||
struct at91_wdt_priv *priv = dev_get_priv(dev); | ||
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priv->regs = dev_remap_addr(dev); | ||
if (!priv->regs) | ||
return -EINVAL; | ||
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#ifdef CONFIG_AT91_HW_WDT_TIMEOUT | ||
priv->timeout = dev_read_u32_default(dev, "timeout-sec", | ||
WDT_DEFAULT_TIMEOUT); | ||
debug("%s: timeout %d", __func__, priv->timeout); | ||
#endif | ||
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debug("%s: Probing wdt%u\n", __func__, dev->seq); | ||
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return 0; | ||
} | ||
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U_BOOT_DRIVER(at91_wdt) = { | ||
.name = "at91_wdt", | ||
.id = UCLASS_WDT, | ||
.of_match = at91_wdt_ids, | ||
.priv_auto_alloc_size = sizeof(struct at91_wdt_priv), | ||
.ops = &at91_wdt_ops, | ||
.probe = at91_wdt_probe, | ||
}; |
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