Merge git://git.denx.de/u-boot-dm

Conflicts:
	drivers/serial/serial-uclass.c

Signed-off-by: Tom Rini <[email protected]>

README

@@ -623,6 +623,120 @@ The following options need to be configured:
 		exists, unlike the similar options in the Linux kernel. Do not
 		set these options unless they apply!
 
+- Driver Model
+		Driver model is a new framework for devices in U-Boot
+		introduced in early 2014. U-Boot is being progressively
+		moved over to this. It offers a consistent device structure,
+		supports grouping devices into classes and has built-in
+		handling of platform data and device tree.
+
+		To enable transition to driver model in a relatively
+		painful fashion, each subsystem can be independently
+		switched between the legacy/ad-hoc approach and the new
+		driver model using the options below. Also, many uclass
+		interfaces include compatibility features which may be
+		removed once the conversion of that subsystem is complete.
+		As a result, the API provided by the subsystem may in fact
+		not change with driver model.
+
+		See doc/driver-model/README.txt for more information.
+
+		CONFIG_DM
+
+		Enable driver model. This brings in the core support,
+		including scanning of platform data on start-up. If
+		CONFIG_OF_CONTROL is enabled, the device tree will be
+		scanned also when available.
+
+		CONFIG_CMD_DM
+
+		Enable driver model test commands. These allow you to print
+		out the driver model tree and the uclasses.
+
+		CONFIG_DM_DEMO
+
+		Enable some demo devices and the 'demo' command. These are
+		really only useful for playing around while trying to
+		understand driver model in sandbox.
+
+		CONFIG_SPL_DM
+
+		Enable driver model in SPL. You will need to provide a
+		suitable malloc() implementation. If you are not using the
+		full malloc() enabled by CONFIG_SYS_SPL_MALLOC_START,
+		consider using CONFIG_SYS_MALLOC_SIMPLE. In that case you
+		must provide CONFIG_SYS_MALLOC_F_LEN to set the size.
+		In most cases driver model will only allocate a few uclasses
+		and devices in SPL, so 1KB should be enable. See
+		CONFIG_SYS_MALLOC_F_LEN for more details on how to enable
+		it.
+
+		CONFIG_DM_SERIAL
+
+		Enable driver model for serial. This replaces
+		drivers/serial/serial.c with the serial uclass, which
+		implements serial_putc() etc. The uclass interface is
+		defined in include/serial.h.
+
+		CONFIG_DM_GPIO
+
+		Enable driver model for GPIO access. The standard GPIO
+		interface (gpio_get_value(), etc.) is then implemented by
+		the GPIO uclass. Drivers provide methods to query the
+		particular GPIOs that they provide. The uclass interface
+		is defined in include/asm-generic/gpio.h.
+
+		CONFIG_DM_SPI
+
+		Enable driver model for SPI. The SPI slave interface
+		(spi_setup_slave(), spi_xfer(), etc.) is then implemented by
+		the SPI uclass. Drivers provide methods to access the SPI
+		buses that they control. The uclass interface is defined in
+		include/spi.h. The existing spi_slave structure is attached
+		as 'parent data' to every slave on each bus. Slaves
+		typically use driver-private data instead of extending the
+		spi_slave structure.
+
+		CONFIG_DM_SPI_FLASH
+
+		Enable driver model for SPI flash. This SPI flash interface
+		(spi_flash_probe(), spi_flash_write(), etc.) is then
+		implemented by the SPI flash uclass. There is one standard
+		SPI flash driver which knows how to probe most chips
+		supported by U-Boot. The uclass interface is defined in
+		include/spi_flash.h, but is currently fully compatible
+		with the old interface to avoid confusion and duplication
+		during the transition parent. SPI and SPI flash must be
+		enabled together (it is not possible to use driver model
+		for one and not the other).
+
+		CONFIG_DM_CROS_EC
+
+		Enable driver model for the Chrome OS EC interface. This
+		allows the cros_ec SPI driver to operate with CONFIG_DM_SPI
+		but otherwise makes few changes. Since cros_ec also supports
+		I2C and LPC (which don't support driver model yet), a full
+		conversion is not yet possible.
+
+
+		** Code size options: The following options are enabled by
+		default except in SPL. Enable them explicitly to get these
+		features in SPL.
+
+		CONFIG_DM_WARN
+
+		Enable the dm_warn() function. This can use up quite a bit
+		of space for its strings.
+
+		CONFIG_DM_STDIO
+
+		Enable registering a serial device with the stdio library.
+
+		CONFIG_DM_DEVICE_REMOVE
+
+		Enable removing of devices.
+
+
 - Linux Kernel Interface:
 		CONFIG_CLOCKS_IN_MHZ
 
@@ -3870,6 +3984,11 @@ Configuration Settings:
 		Pre-relocation malloc() is only supported on ARM and sandbox
 		at present but is fairly easy to enable for other archs.
 
+- CONFIG_SYS_MALLOC_SIMPLE
+		Provides a simple and small malloc() and calloc() for those
+		boards which do not use the full malloc in SPL (which is
+		enabled with CONFIG_SYS_SPL_MALLOC_START).
+
 - CONFIG_SYS_BOOTM_LEN:
 		Normally compressed uImages are limited to an
 		uncompressed size of 8 MBytes. If this is not enough,

arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c

@@ -7,6 +7,7 @@
  */
 
 #include <common.h>
+#include <dm.h>
 #include <asm/io.h>
 #include <asm/arch/at91sam9260_matrix.h>
 #include <asm/arch/at91_common.h>
@@ -229,3 +230,16 @@ void at91_sdram_hw_init(void)
 	at91_set_a_periph(AT91_PIO_PORTC, 30, 0);
 	at91_set_a_periph(AT91_PIO_PORTC, 31, 0);
 }
+
+/* Platform data for the GPIOs */
+static const struct at91_port_platdata at91sam9260_plat[] = {
+	{ ATMEL_BASE_PIOA, "PA" },
+	{ ATMEL_BASE_PIOB, "PB" },
+	{ ATMEL_BASE_PIOC, "PC" },
+};
+
+U_BOOT_DEVICES(at91sam9260_gpios) = {
+	{ "gpio_at91", &at91sam9260_plat[0] },
+	{ "gpio_at91", &at91sam9260_plat[1] },
+	{ "gpio_at91", &at91sam9260_plat[2] },
+};

arch/arm/cpu/u-boot-spl.lds

@@ -34,6 +34,13 @@ SECTIONS
 	. = ALIGN(4);
 
 	. = .;
+#ifdef CONFIG_SPL_DM
+	.u_boot_list : {
+		KEEP(*(SORT(.u_boot_list_*_driver_*)));
+		KEEP(*(SORT(.u_boot_list_*_uclass_*)));
+	}
+#endif
+	. = ALIGN(4);
 
 	__image_copy_end = .;
 

arch/arm/include/asm/arch-at91/at91sam9260.h

@@ -136,9 +136,11 @@
 /*
  * Other misc defines
  */
+#ifndef CONFIG_DM_GPIO
 #define ATMEL_PIO_PORTS		3		/* these SoCs have 3 PIO */
-#define ATMEL_PMC_UHP		AT91SAM926x_PMC_UHP
 #define ATMEL_BASE_PIO		ATMEL_BASE_PIOA
+#endif
+#define ATMEL_PMC_UHP		AT91SAM926x_PMC_UHP
 
 /*
  * SoC specific defines

arch/arm/include/asm/arch-at91/atmel_serial.h

@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _ATMEL_SERIAL_H
+#define _ATMEL_SERIAL_H
+
+/* Information about a serial port */
+struct atmel_serial_platdata {
+	uint32_t base_addr;
+};
+
+#endif

arch/arm/include/asm/arch-at91/gpio.h

@@ -253,4 +253,10 @@ static inline unsigned at91_gpio_to_pin(unsigned gpio)
 	return gpio % 32;
 }
 
+/* Platform data for each GPIO port */
+struct at91_port_platdata {
+	uint32_t base_addr;
+	const char *bank_name;
+};
+
 #endif /* __ASM_ARCH_AT91_GPIO_H */

arch/arm/lib/crt0.S

@@ -78,7 +78,7 @@ clr_gd:
 	strlo	r0, [r1]		/* clear 32-bit GD word */
 	addlo	r1, r1, #4		/* move to next */
 	blo	clr_gd
-#if defined(CONFIG_SYS_MALLOC_F_LEN) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_SYS_MALLOC_F_LEN)
 	sub	sp, sp, #CONFIG_SYS_MALLOC_F_LEN
 	str	sp, [r9, #GD_MALLOC_BASE]
 #endif

board/bluewater/snapper9260/MAINTAINERS

@@ -1,5 +1,5 @@
 SNAPPER9260 BOARD
-M:	Ryan Mallon <[email protected]>
+M:	Simon Glass <[email protected]>
 S:	Maintained
 F:	board/bluewater/snapper9260/
 F:	include/configs/snapper9260.h

board/bluewater/snapper9260/snapper9260.c

@@ -9,12 +9,15 @@
  */
 
 #include <common.h>
+#include <dm.h>
 #include <asm/io.h>
+#include <asm/gpio.h>
 #include <asm/arch/at91sam9260_matrix.h>
 #include <asm/arch/at91sam9_smc.h>
 #include <asm/arch/at91_common.h>
 #include <asm/arch/at91_pmc.h>
 #include <asm/arch/gpio.h>
+#include <asm/arch/atmel_serial.h>
 #include <net.h>
 #include <netdev.h>
 #include <i2c.h>
@@ -95,10 +98,12 @@ static void nand_hw_init(void)
 	       &smc->cs[3].mode);
 
 	/* Configure RDY/BSY */
-	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+	gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand_rdy");
+	gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
 
 	/* Enable NandFlash */
-	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+	gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand_ce");
+	gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
 }
 
 int board_init(void)
@@ -140,3 +145,12 @@ int dram_init(void)
 void reset_phy(void)
 {
 }
+
+static struct atmel_serial_platdata at91sam9260_serial_plat = {
+	.base_addr = ATMEL_BASE_DBGU,
+};
+
+U_BOOT_DEVICE(at91sam9260_serial) = {
+	.name	= "serial_atmel",
+	.platdata = &at91sam9260_serial_plat,
+};

board/nvidia/common/board.c

@@ -6,6 +6,7 @@
  */
 
 #include <common.h>
+#include <dm.h>
 #include <ns16550.h>
 #include <linux/compiler.h>
 #include <asm/io.h>
@@ -43,6 +44,13 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifdef CONFIG_SPL_BUILD
+/* TODO([email protected]): Remove once SPL supports device tree */
+U_BOOT_DEVICE(tegra_gpios) = {
+	"gpio_tegra"
+};
+#endif
+
 const struct tegra_sysinfo sysinfo = {
 	CONFIG_TEGRA_BOARD_STRING
 };

common/Makefile

@@ -252,6 +252,9 @@ obj-$(CONFIG_BOUNCE_BUFFER) += bouncebuf.o
 obj-y += console.o
 obj-$(CONFIG_CROS_EC) += cros_ec.o
 obj-y += dlmalloc.o
+ifdef CONFIG_SYS_MALLOC_F_LEN
+obj-y += malloc_simple.o
+endif
 obj-y += image.o
 obj-$(CONFIG_ANDROID_BOOT_IMAGE) += image-android.o
 obj-$(CONFIG_OF_LIBFDT) += image-fdt.o

common/board_r.c

@@ -99,7 +99,8 @@ static int initr_trace(void)
 
 static int initr_reloc(void)
 {
-	gd->flags |= GD_FLG_RELOC;	/* tell others: relocation done */
+	/* tell others: relocation done */
+	gd->flags |= GD_FLG_RELOC | GD_FLG_FULL_MALLOC_INIT;
 	bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_R, "board_init_r");
 
 	return 0;