Merge tag 'xilinx-for-v2020.07' of https://gitlab.denx.de/u-boot/cust…

…odians/u-boot-microblaze into next

Xilinx changes for v2020.07

common:
- Align ENV_FAT_INTERFACE
- Fix MAC address source print log
- Improve based autodetection code

xilinx:
- Enable netconsole

Microblaze:
- Setup default ENV_OFFSET/ENV_SECT_SIZE

Zynq:
- Multiple DT updates/fixes
- Use DEVICE_TREE environment variable for DTB selection
- Switch to single zynq configuration
- Enable NOR flash via DM
- Minor SPL print removal
- Enable i2c mux driver

ZynqMP:
- Print multiboot register
- Enable cache commands in mini mtest
- Multiple DT updates/fixes
- Fix firmware probing when driver is not enabled
- Specify 3rd backup RAM boot mode in SPL
- Add SPL support for zcu102 v1.1 and zcu111 revA
- Redesign debug uart enabling and psu_init delay
- Enable full u-boot run from EL3
- Enable u-boot.itb generation without ATF with U-Boot in EL3

Versal:
- Enable distro default
- Enable others SPI flashes
- Enable systems without DDR

Drivers:
- Gem:
  - Flush memory after freeing
  - Handle mdio bus separately
- Watchdog:
  - Get rid of unused global data pointer
  - Enable window watchdog timer
- Serial:
  - Change reinitialization logic in zynq serial driver

Signed-off-by: Tom Rini <[email protected]>

.azure-pipelines.yml

@@ -228,11 +228,11 @@ jobs:
           TEST_PY_BD: "qemu-x86_64"
           TEST_PY_TEST_SPEC: "not sleep"
           BUILDMAN: "^qemu-x86_64$"
-        zynq_zc702:
-          TEST_PY_BD: "zynq_zc702"
+        xilinx_zynq_virt:
+          TEST_PY_BD: "xilinx_zynq_virt"
           TEST_PY_ID: "--id qemu"
           TEST_PY_TEST_SPEC: "not sleep"
-          BUILDMAN: "^zynq_zc702$"
+          BUILDMAN: "^xilinx_zynq_virt$"
         xilinx_versal_virt:
           TEST_PY_BD: "xilinx_versal_virt"
           TEST_PY_ID: "--id qemu"

.gitlab-ci.yml

@@ -321,13 +321,13 @@ qemu-x86_64 test.py:
     BUILDMAN: "^qemu-x86_64$"
   <<: *buildman_and_testpy_dfn
 
-zynq_zc702 test.py:
+xilinx_zynq_virt test.py:
   tags: [ 'all' ]
   variables:
-    TEST_PY_BD: "zynq_zc702"
+    TEST_PY_BD: "xilinx_zynq_virt"
     TEST_PY_TEST_SPEC: "not sleep"
     TEST_PY_ID: "--id qemu"
-    BUILDMAN: "^zynq_zc702$"
+    BUILDMAN: "^xilinx_zynq_virt$"
   <<: *buildman_and_testpy_dfn
 
 xilinx_versal_virt test.py:

.travis.yml

@@ -505,13 +505,13 @@ matrix:
           BUILDMAN="^qemu-x86_64$"
           TOOLCHAIN="i386"
           BUILD_ROM="yes"
-    - name: "test/py zynq_zc702"
+    - name: "test/py xilinx_zynq_virt"
       env:
-        - TEST_PY_BD="zynq_zc702"
+        - TEST_PY_BD="xilinx_zynq_virt"
           TEST_PY_TEST_SPEC="not sleep"
           QEMU_TARGET="arm-softmmu"
           TEST_PY_ID="--id qemu"
-          BUILDMAN="^zynq_zc702$"
+          BUILDMAN="^xilinx_zynq_virt$"
     - name: "test/py xilinx_versal_virt"
       env:
         - TEST_PY_BD="xilinx_versal_virt"

Kconfig

@@ -111,6 +111,7 @@ config ENV_VARS_UBOOT_CONFIG
 
 config NR_DRAM_BANKS
 	int "Number of DRAM banks"
+	default 1 if ARCH_SUNXI
 	default 4
 	help
 	  This defines the number of DRAM banks.
@@ -294,6 +295,11 @@ config ERR_PTR_OFFSET
 	  pointer values - up to 'MAX_ERRNO' bytes below this value must be
 	  unused/invalid addresses.
 
+config PLATFORM_ELFENTRY
+	string
+	default "__start" if MIPS
+	default "_start"
+
 endmenu		# General setup
 
 menu "Boot images"

MAINTAINERS

@@ -447,6 +447,7 @@ M:	Michal Simek <[email protected]>
 S:	Maintained
 T:	git https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze.git
 F:	arch/arm/mach-versal/
+F:	drivers/watchdog/xilinx_wwdt.c
 N:	(?<!uni)versal
 
 ARM VERSATILE EXPRESS DRIVERS

Makefile

@@ -3,7 +3,7 @@
 VERSION = 2020
 PATCHLEVEL = 04
 SUBLEVEL =
-EXTRAVERSION = -rc3
+EXTRAVERSION = -rc4
 NAME =
 
 # *DOCUMENTATION*
@@ -485,6 +485,7 @@ endif
 version_h := include/generated/version_autogenerated.h
 timestamp_h := include/generated/timestamp_autogenerated.h
 defaultenv_h := include/generated/defaultenv_autogenerated.h
+dt_h := include/generated/dt.h
 
 no-dot-config-targets := clean clobber mrproper distclean \
 			 help %docs check% coccicheck \
@@ -1654,18 +1655,17 @@ OBJCOPYFLAGS_u-boot-img-spl-at-end.bin := -I binary -O binary \
 u-boot-img-spl-at-end.bin: u-boot.img spl/u-boot-spl.bin FORCE
 	$(call if_changed,pad_cat)
 
-# Create a new ELF from a raw binary file.
-ifndef PLATFORM_ELFENTRY
-  PLATFORM_ELFENTRY = "_start"
-endif
 quiet_cmd_u-boot-elf ?= LD      $@
 	cmd_u-boot-elf ?= $(LD) u-boot-elf.o -o $@ \
-	--defsym=$(PLATFORM_ELFENTRY)=$(CONFIG_SYS_TEXT_BASE) \
+	-T u-boot-elf.lds --defsym=$(CONFIG_PLATFORM_ELFENTRY)=$(CONFIG_SYS_TEXT_BASE) \
 	-Ttext=$(CONFIG_SYS_TEXT_BASE)
-u-boot.elf: u-boot.bin
+u-boot.elf: u-boot.bin u-boot-elf.lds
 	$(Q)$(OBJCOPY) -I binary $(PLATFORM_ELFFLAGS) $< u-boot-elf.o
 	$(call if_changed,u-boot-elf)
 
+u-boot-elf.lds: arch/u-boot-elf.lds prepare FORCE
+	$(call if_changed_dep,cpp_lds)
+
 # MediaTek's ARM-based u-boot needs a header to contains its load address
 # which is parsed by the BootROM.
 # If the SPL build is enabled, the header will be added to the spl binary,
@@ -1775,7 +1775,7 @@ endif
 # prepare2 creates a makefile if using a separate output directory
 prepare2: prepare3 outputmakefile cfg
 
-prepare1: prepare2 $(version_h) $(timestamp_h) \
+prepare1: prepare2 $(version_h) $(timestamp_h) $(dt_h) \
                    include/config/auto.conf
 ifeq ($(wildcard $(LDSCRIPT)),)
 	@echo >&2 "  Could not find linker script."
@@ -1841,12 +1841,23 @@ define filechk_defaultenv.h
 	 xxd -i ; echo ", 0x00" ; )
 endef
 
+define filechk_dt.h
+	(if test -n "$${DEVICE_TREE}"; then \
+		echo \#define DEVICE_TREE \"$(DEVICE_TREE)\"; \
+	else \
+		echo \#define DEVICE_TREE CONFIG_DEFAULT_DEVICE_TREE; \
+	fi)
+endef
+
 $(version_h): include/config/uboot.release FORCE
 	$(call filechk,version.h)
 
 $(timestamp_h): $(srctree)/Makefile FORCE
 	$(call filechk,timestamp.h)
 
+$(dt_h): $(srctree)/Makefile FORCE
+	$(call filechk,dt.h)
+
 $(defaultenv_h): $(CONFIG_DEFAULT_ENV_FILE:"%"=%) FORCE
 	$(call filechk,defaultenv.h)
 

arch/arc/include/asm/io.h

@@ -9,6 +9,12 @@
 #include <linux/types.h>
 #include <asm/byteorder.h>
 
+/*
+ * Compiler barrier. It prevents compiler from reordering instructions before
+ * and after it. It doesn't prevent HW (CPU) from any reordering though.
+ */
+#define __comp_b()		asm volatile("" : : : "memory")
+
 #ifdef __ARCHS__
 
 /*
@@ -45,40 +51,56 @@
 #define __iormb()		rmb()
 #define __iowmb()		wmb()
 #else
-#define __iormb()		asm volatile("" : : : "memory")
-#define __iowmb()		asm volatile("" : : : "memory")
+#define __iormb()		__comp_b()
+#define __iowmb()		__comp_b()
 #endif
 
 static inline void sync(void)
 {
 	/* Not yet implemented */
 }
 
-#define __arch_getb(a)		(*(unsigned char *)(a))
-#define __arch_getw(a)		(*(unsigned short *)(a))
-#define __arch_getl(a)		(*(unsigned int *)(a))
-#define __arch_getq(a)		(*(unsigned long long *)(a))
+/*
+ * We must use 'volatile' in C-version read/write IO accessors implementation
+ * to avoid merging several reads (writes) into one read (write), or optimizing
+ * them out by compiler.
+ * We must use compiler barriers before and after operation (read or write) so
+ * it won't be reordered by compiler.
+ */
+#define __arch_getb(a)		({ u8  __v; __comp_b(); __v = *(volatile u8  *)(a); __comp_b(); __v; })
+#define __arch_getw(a)		({ u16 __v; __comp_b(); __v = *(volatile u16 *)(a); __comp_b(); __v; })
+#define __arch_getl(a)		({ u32 __v; __comp_b(); __v = *(volatile u32 *)(a); __comp_b(); __v; })
+#define __arch_getq(a)		({ u64 __v; __comp_b(); __v = *(volatile u64 *)(a); __comp_b(); __v; })
+
+#define __arch_putb(v, a)	({ __comp_b(); *(volatile u8  *)(a) = (v); __comp_b(); })
+#define __arch_putw(v, a)	({ __comp_b(); *(volatile u16 *)(a) = (v); __comp_b(); })
+#define __arch_putl(v, a)	({ __comp_b(); *(volatile u32 *)(a) = (v); __comp_b(); })
+#define __arch_putq(v, a)	({ __comp_b(); *(volatile u64 *)(a) = (v); __comp_b(); })
 
-#define __arch_putb(v, a)	(*(unsigned char *)(a) = (v))
-#define __arch_putw(v, a)	(*(unsigned short *)(a) = (v))
-#define __arch_putl(v, a)	(*(unsigned int *)(a) = (v))
-#define __arch_putq(v, a)	(*(unsigned long long *)(a) = (v))
 
-#define __raw_writeb(v, a)	__arch_putb(v, a)
-#define __raw_writew(v, a)	__arch_putw(v, a)
-#define __raw_writel(v, a)	__arch_putl(v, a)
-#define __raw_writeq(v, a)	__arch_putq(v, a)
+/*
+ * We add memory barriers for __raw_readX / __raw_writeX accessors same way as
+ * it is done for readX and writeX accessors as lots of U-boot driver uses
+ * __raw_readX / __raw_writeX instead of proper accessor with barrier.
+ */
+#define __raw_writeb(v, c)	({ __iowmb(); __arch_putb(v, c); })
+#define __raw_writew(v, c)	({ __iowmb(); __arch_putw(v, c); })
+#define __raw_writel(v, c)	({ __iowmb(); __arch_putl(v, c); })
+#define __raw_writeq(v, c)	({ __iowmb(); __arch_putq(v, c); })
+
+#define __raw_readb(c)		({ u8  __v = __arch_getb(c); __iormb(); __v; })
+#define __raw_readw(c)		({ u16 __v = __arch_getw(c); __iormb(); __v; })
+#define __raw_readl(c)		({ u32 __v = __arch_getl(c); __iormb(); __v; })
+#define __raw_readq(c)		({ u64 __v = __arch_getq(c); __iormb(); __v; })
 
-#define __raw_readb(a)		__arch_getb(a)
-#define __raw_readw(a)		__arch_getw(a)
-#define __raw_readl(a)		__arch_getl(a)
-#define __raw_readq(a)		__arch_getq(a)
 
 static inline void __raw_writesb(unsigned long addr, const void *data,
 				 int bytelen)
 {
 	u8 *buf = (uint8_t *)data;
 
+	__iowmb();
+
 	while (bytelen--)
 		__arch_putb(*buf++, addr);
 }
@@ -88,6 +110,8 @@ static inline void __raw_writesw(unsigned long addr, const void *data,
 {
 	u16 *buf = (uint16_t *)data;
 
+	__iowmb();
+
 	while (wordlen--)
 		__arch_putw(*buf++, addr);
 }
@@ -97,6 +121,8 @@ static inline void __raw_writesl(unsigned long addr, const void *data,
 {
 	u32 *buf = (uint32_t *)data;
 
+	__iowmb();
+
 	while (longlen--)
 		__arch_putl(*buf++, addr);
 }
@@ -107,6 +133,8 @@ static inline void __raw_readsb(unsigned long addr, void *data, int bytelen)
 
 	while (bytelen--)
 		*buf++ = __arch_getb(addr);
+
+	__iormb();
 }
 
 static inline void __raw_readsw(unsigned long addr, void *data, int wordlen)
@@ -115,6 +143,8 @@ static inline void __raw_readsw(unsigned long addr, void *data, int wordlen)
 
 	while (wordlen--)
 		*buf++ = __arch_getw(addr);
+
+	__iormb();
 }
 
 static inline void __raw_readsl(unsigned long addr, void *data, int longlen)
@@ -123,28 +153,24 @@ static inline void __raw_readsl(unsigned long addr, void *data, int longlen)
 
 	while (longlen--)
 		*buf++ = __arch_getl(addr);
+
+	__iormb();
 }
 
 /*
  * Relaxed I/O memory access primitives. These follow the Device memory
  * ordering rules but do not guarantee any ordering relative to Normal memory
  * accesses.
  */
-#define readb_relaxed(c)	({ u8  __r = __raw_readb(c); __r; })
-#define readw_relaxed(c)	({ u16 __r = le16_to_cpu((__force __le16) \
-						__raw_readw(c)); __r; })
-#define readl_relaxed(c)	({ u32 __r = le32_to_cpu((__force __le32) \
-						__raw_readl(c)); __r; })
-#define readq_relaxed(c)	({ u64 __r = le64_to_cpu((__force __le64) \
-						__raw_readq(c)); __r; })
-
-#define writeb_relaxed(v, c)	((void)__raw_writeb((v), (c)))
-#define writew_relaxed(v, c)	((void)__raw_writew((__force u16) \
-						    cpu_to_le16(v), (c)))
-#define writel_relaxed(v, c)	((void)__raw_writel((__force u32) \
-						    cpu_to_le32(v), (c)))
-#define writeq_relaxed(v, c)	((void)__raw_writeq((__force u64) \
-						    cpu_to_le64(v), (c)))
+#define readb_relaxed(c)	({ u8  __r = __arch_getb(c); __r; })
+#define readw_relaxed(c)	({ u16 __r = le16_to_cpu((__force __le16)__arch_getw(c)); __r; })
+#define readl_relaxed(c)	({ u32 __r = le32_to_cpu((__force __le32)__arch_getl(c)); __r; })
+#define readq_relaxed(c)	({ u64 __r = le64_to_cpu((__force __le64)__arch_getq(c)); __r; })
+
+#define writeb_relaxed(v, c)	((void)__arch_putb((v), (c)))
+#define writew_relaxed(v, c)	((void)__arch_putw((__force u16)cpu_to_le16(v), (c)))
+#define writel_relaxed(v, c)	((void)__arch_putl((__force u32)cpu_to_le32(v), (c)))
+#define writeq_relaxed(v, c)	((void)__arch_putq((__force u64)cpu_to_le64(v), (c)))
 
 /*
  * MMIO can also get buffered/optimized in micro-arch, so barriers needed

arch/arm/Kconfig

@@ -989,6 +989,8 @@ config ARCH_SUNXI
 	select USB_KEYBOARD if DISTRO_DEFAULTS
 	select USB_STORAGE if DISTRO_DEFAULTS
 	select SPL_USE_TINY_PRINTF
+	select USE_PREBOOT
+	select SYS_RELOC_GD_ENV_ADDR
 	imply CMD_DM
 	imply CMD_GPT
 	imply CMD_UBI if MTD_RAW_NAND
@@ -1366,6 +1368,7 @@ config TARGET_LS1028ARDB
 	select ARM64
 	select ARMV8_MULTIENTRY
 	select ARCH_SUPPORT_TFABOOT
+	select BOARD_LATE_INIT
 	help
 	  Support for Freescale LS1028ARDB platform
 	  The LS1028A Development System (RDB) is a high-performance

arch/arm/cpu/armv8/cpu.c

@@ -32,6 +32,8 @@ void sdelay(unsigned long loops)
 			  "b.ne 1b" : "=r" (loops) : "0"(loops) : "cc");
 }
 
+void __weak board_cleanup_before_linux(void){}
+
 int cleanup_before_linux(void)
 {
 	/*
@@ -40,6 +42,9 @@ int cleanup_before_linux(void)
 	 *
 	 * disable interrupt and turn off caches etc ...
 	 */
+
+	board_cleanup_before_linux();
+
 	disable_interrupts();
 
 	/*

arch/arm/cpu/armv8/fsl-layerscape/Kconfig

@@ -74,11 +74,11 @@ config ARCH_LS1043A
 	select SYS_FSL_HAS_DDR4
 	select ARCH_EARLY_INIT_R
 	select BOARD_EARLY_INIT_F
-	select SYS_I2C_MXC
-	select SYS_I2C_MXC_I2C1
-	select SYS_I2C_MXC_I2C2
-	select SYS_I2C_MXC_I2C3
-	select SYS_I2C_MXC_I2C4
+	select SYS_I2C_MXC if !DM_I2C
+	select SYS_I2C_MXC_I2C1 if !DM_I2C
+	select SYS_I2C_MXC_I2C2 if !DM_I2C
+	select SYS_I2C_MXC_I2C3 if !DM_I2C
+	select SYS_I2C_MXC_I2C4 if !DM_I2C
 	imply CMD_PCI
 
 config ARCH_LS1046A
@@ -107,11 +107,11 @@ config ARCH_LS1046A
 	select SYS_FSL_SRDS_2
 	select ARCH_EARLY_INIT_R
 	select BOARD_EARLY_INIT_F
-	select SYS_I2C_MXC
-	select SYS_I2C_MXC_I2C1
-	select SYS_I2C_MXC_I2C2
-	select SYS_I2C_MXC_I2C3
-	select SYS_I2C_MXC_I2C4
+	select SYS_I2C_MXC if !DM_I2C
+	select SYS_I2C_MXC_I2C1 if !DM_I2C
+	select SYS_I2C_MXC_I2C2 if !DM_I2C
+	select SYS_I2C_MXC_I2C3 if !DM_I2C
+	select SYS_I2C_MXC_I2C4 if !DM_I2C
 	imply SCSI
 	imply SCSI_AHCI