Flex bus definition update for Coldfire 5253.

originally work by Jate Sujjavanich <[email protected]> ---- The defines in arch/m68k/include/coldfire/flexbus.h are not compatible with the 5235 processor. The registers in struct fbcs are different sizes from those in the 5235. Also, the defines are a little different. This is what I have so far. Comments? ---- Reformat the patch manually by Jason Jin Signed-off-by: Jate Sujjavanich <[email protected]> Signed-off-by: Jason Jin <[email protected]>
imaami · Sep 20, 2012 · 30a3f38 · 30a3f38
1 parent 59d0612
commit 30a3f38
Showing 1 changed file with 68 additions and 0 deletions.
diff --git a/arch/m68k/include/asm/coldfire/flexbus.h b/arch/m68k/include/asm/coldfire/flexbus.h
@@ -29,7 +29,57 @@
 /*********************************************************************
 * FlexBus Chip Selects (FBCS)
 *********************************************************************/
+#ifdef CONFIG_M5235
+typedef struct fbcs {
+    u16 csar0;      /* Chip-select Address */
+    u16 res1;
+    u32 csmr0;      /* Chip-select Mask */
+    u16 res2;
+    u16 cscr0;      /* Chip-select Control */
+
+    u16 csar1;
+    u16 res3;
+    u32 csmr1;
+    u16 res4;
+    u16 cscr1;
+
+    u16 csar2;
+    u16 res5;
+    u32 csmr2;
+    u16 res6;
+    u16 cscr2;
+
+    u16 csar3;
+    u16 res7;
+    u32 csmr3;
+    u16 res8;
+    u16 cscr3;
+
+    u16 csar4;
+    u16 res9;
+    u32 csmr4;
+    u16 res10;
+    u16 cscr4;
+
+    u16 csar5;
+    u16 res11;
+    u32 csmr5;
+    u16 res12;
+    u16 cscr5;
 
+    u16 csar6;
+    u16 res13;
+    u32 csmr6;
+    u16 res14;
+    u16 cscr6;
+
+    u16 csar7;
+    u16 res15;
+    u32 csmr7;
+    u16 res16;
+    u16 cscr7;
+} fbcs_t;
+#else
 typedef struct fbcs {
 	u32 csar0;		/* Chip-select Address */
 	u32 csmr0;		/* Chip-select Mask */
@@ -56,6 +106,7 @@ typedef struct fbcs {
 	u32 csmr7;
 	u32 cscr7;
 } fbcs_t;
+#endif
 
 #define FBCS_CSAR_BA(x)			((x) & 0xFFFF0000)
 
@@ -94,6 +145,22 @@ typedef struct fbcs {
 #endif
 #define FBCS_CSMR_V			(0x00000001)	/* Valid bit */
 
+#ifdef CONFIG_M5235
+#define FBCS_CSCR_SRWS(x)       (((x) & 0x3) << 14)
+#define FBCS_CSCR_IWS(x)        (((x) & 0xF) << 10)
+#define FBCS_CSCR_AA_ON         (1 << 8)
+#define FBCS_CSCR_AA_OFF        (0 << 8)
+#define FBCS_CSCR_PS_32         (0 << 6)
+#define FBCS_CSCR_PS_16         (2 << 6)
+#define FBCS_CSCR_PS_8          (1 << 6)
+#define FBCS_CSCR_BEM_ON        (1 << 5)
+#define FBCS_CSCR_BEM_OFF       (0 << 5)
+#define FBCS_CSCR_BSTR_ON       (1 << 4)
+#define FBCS_CSCR_BSTR_OFF      (0 << 4)
+#define FBCS_CSCR_BSTW_ON       (1 << 3)
+#define FBCS_CSCR_BSTW_OFF      (0 << 3)
+#define FBCS_CSCR_SWWS(x)       (((x) & 0x7) << 0)
+#else
 #define FBCS_CSCR_SWS(x)		(((x) & 0x3F) << 26)
 #define FBCS_CSCR_SWS_MASK		(0x03FFFFFF)
 #define FBCS_CSCR_SWSEN			(0x00800000)
@@ -116,5 +183,6 @@ typedef struct fbcs {
 #define FBCS_CSCR_PS_16			(0x00000080)
 #define FBCS_CSCR_PS_8			(0x00000040)
 #define FBCS_CSCR_PS_32			(0x00000000)
+#endif
 
 #endif				/* __FLEXBUS_H */